| Message ID | 1274367150-26576-3-git-send-email-froydnj@codesourcery.com |
|---|---|
| State | New |
| Headers | show |
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 7285636..986d938 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -363,6 +363,9 @@ struct CPUMIPSState { #define CP0C2_SA 0 int32_t CP0_Config3; #define CP0C3_M 31 +#define CP0C3_ISA_ON_EXC 16 +#define CP0C3_ISA 14 +#define CP0C3_DSP2P 11 #define CP0C3_DSPP 10 #define CP0C3_LPA 7 #define CP0C3_VEIC 6 diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h index c57de02..a7f4697 100644 --- a/target-mips/mips-defs.h +++ b/target-mips/mips-defs.h @@ -38,6 +38,7 @@ #define ASE_DSPR2 0x00010000 #define ASE_MT 0x00020000 #define ASE_SMARTMIPS 0x00040000 +#define ASE_MICROMIPS 0x00080000 /* Chip specific instructions. */ #define INSN_VR54XX 0x80000000
There's a new ASE_MICROMIPS instruction flag, and some extra CP0_Config3 fields. The ISA and ISA_ON_EXC fields are specific to microMIPS. The DSP2P is for version 2 of the DSP ASE. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> --- target-mips/cpu.h | 3 +++ target-mips/mips-defs.h | 1 + 2 files changed, 4 insertions(+), 0 deletions(-)