From patchwork Wed Apr 7 17:51:18 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 49625 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 25B4FB7D08 for ; Thu, 8 Apr 2010 04:16:21 +1000 (EST) Received: from localhost ([127.0.0.1]:58339 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NzZeH-00021G-Hp for incoming@patchwork.ozlabs.org; Wed, 07 Apr 2010 14:06:45 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NzZQF-0006Ac-Ft for qemu-devel@nongnu.org; Wed, 07 Apr 2010 13:52:15 -0400 Received: from [140.186.70.92] (port=55359 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NzZPx-00062R-SA for qemu-devel@nongnu.org; Wed, 07 Apr 2010 13:52:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1NzZPi-0007Jp-OK for qemu-devel@nongnu.org; Wed, 07 Apr 2010 13:51:56 -0400 Received: from hall.aurel32.net ([88.191.82.174]:45321) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1NzZPi-0007J4-FC for qemu-devel@nongnu.org; Wed, 07 Apr 2010 13:51:42 -0400 Received: from [2a01:e35:2e80:2fb0:21e:8cff:feb0:693b] (helo=volta.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1NzZPh-00011V-IV; Wed, 07 Apr 2010 19:51:41 +0200 Received: from aurel32 by volta.aurel32.net with local (Exim 4.71) (envelope-from ) id 1NzZPc-0001y4-Fu; Wed, 07 Apr 2010 19:51:36 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Wed, 7 Apr 2010 19:51:18 +0200 Message-Id: <1270662685-7379-12-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1270662685-7379-1-git-send-email-aurelien@aurel32.net> References: <1270662685-7379-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: Andrzej Zaborowski , Aurelien Jarno Subject: [Qemu-devel] [PATCH 11/18] tcg/arm: add bswap ops X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add an bswap16 and bswap32 ops, either using the rev and rev16 instructions on ARMv6+ or shifts and logical operations on previous ARM versions. In both cases the result use less instructions than the pure TCG version. These ops are also needed by the qemu_ld/st functions. Signed-off-by: Aurelien Jarno --- tcg/arm/tcg-target.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ tcg/arm/tcg-target.h | 4 ++-- 2 files changed, 50 insertions(+), 2 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index d8ba5f1..aec1183 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -503,6 +503,44 @@ static inline void tcg_out_ext16u(TCGContext *s, int cond, #endif } +static inline void tcg_out_bswap16(TCGContext *s, int cond, int rd, int rn) +{ +#ifdef USE_ARMV6_INSTRUCTIONS + /* rev16 */ + tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn); +#else + tcg_out_dat_reg(s, cond, ARITH_MOV, + TCG_REG_R8, 0, rn, SHIFT_IMM_LSL(24)); + tcg_out_dat_reg(s, cond, ARITH_MOV, + TCG_REG_R8, 0, TCG_REG_R8, SHIFT_IMM_LSR(16)); + tcg_out_dat_reg(s, cond, ARITH_ORR, + rd, TCG_REG_R8, rn, SHIFT_IMM_LSR(8)); +#endif +} + +static inline void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn) +{ +#ifdef USE_ARMV6_INSTRUCTIONS + /* rev */ + tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn); +#else + /* This code only uses one temporary register. There is probably + a faster way to do that with more temporary registers. */ + tcg_out_dat_reg(s, cond, ARITH_MOV, + TCG_REG_R8, 0, rn, SHIFT_IMM_ROR(8)); + tcg_out_dat_imm(s, cond, ARITH_BIC, + rd, TCG_REG_R8, 0xff); + tcg_out_dat_imm(s, cond, ARITH_BIC, + rd, rd, 0xff | 0x800); + tcg_out_dat_imm(s, cond, ARITH_BIC, + TCG_REG_R8, TCG_REG_R8, 0xff | 0x400); + tcg_out_dat_imm(s, cond, ARITH_BIC, + TCG_REG_R8, TCG_REG_R8, 0xff | 0xc00); + tcg_out_dat_reg(s, cond, ARITH_ORR, + rd, rd, TCG_REG_R8, SHIFT_IMM_ROR(16)); +#endif +} + static inline void tcg_out_ld32_12(TCGContext *s, int cond, int rd, int rn, tcg_target_long im) { @@ -1520,6 +1558,13 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_qemu_st(s, COND_AL, args, 3); break; + case INDEX_op_bswap16_i32: + tcg_out_bswap16(s, COND_AL, args[0], args[1]); + break; + case INDEX_op_bswap32_i32: + tcg_out_bswap32(s, COND_AL, args[0], args[1]); + break; + case INDEX_op_ext8s_i32: tcg_out_ext8s(s, COND_AL, args[0], args[1]); break; @@ -1607,6 +1652,9 @@ static const TCGTargetOpDef arm_op_defs[] = { { INDEX_op_qemu_st64, { "x", "D", "x", "X" } }, #endif + { INDEX_op_bswap16_i32, { "r", "r" } }, + { INDEX_op_bswap32_i32, { "r", "r" } }, + { INDEX_op_ext8s_i32, { "r", "r" } }, { INDEX_op_ext16s_i32, { "r", "r" } }, { INDEX_op_ext16u_i32, { "r", "r" } }, diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 1f6d665..d8d7d94 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -62,8 +62,8 @@ enum { #define TCG_TARGET_HAS_ext16s_i32 #undef TCG_TARGET_HAS_ext8u_i32 /* and r0, r1, #0xff */ #define TCG_TARGET_HAS_ext16u_i32 -// #define TCG_TARGET_HAS_bswap16_i32 -// #define TCG_TARGET_HAS_bswap32_i32 +#define TCG_TARGET_HAS_bswap16_i32 +#define TCG_TARGET_HAS_bswap32_i32 #define TCG_TARGET_HAS_not_i32 #define TCG_TARGET_HAS_neg_i32 #define TCG_TARGET_HAS_rot_i32