diff mbox

mips: No MIPS16 support for 4Kc, 4KEc cores

Message ID 1260882183-7398-1-git-send-email-weil@mail.berlios.de
State New
Headers show

Commit Message

Stefan Weil Dec. 15, 2009, 1:03 p.m. UTC 
Fix regression introduced by d19954f46dfc262612c30e9534e660e953049487.

4Kc and 4KEc don't support MIPS16.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
---
 target-mips/translate_init.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

Comments

Nathan Froyd Dec. 15, 2009, 1:22 p.m. UTC | #1 
On Tue, Dec 15, 2009 at 02:03:03PM +0100, Stefan Weil wrote:
> Fix regression introduced by d19954f46dfc262612c30e9534e660e953049487.
> 
> 4Kc and 4KEc don't support MIPS16.

Nice catch.  Can you please also remove ASE_MIPS16 from .insn_flags for
those same CPUs, then?

Thanks,
-Nathan
diff mbox

Patch

diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 11bc47c..b710979 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -105,7 +105,7 @@  static const mips_def_t mips_defs[] =
         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
                        (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
                        (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
-                       (1 << CP0C1_CA),
+                       (0 << CP0C1_CA),
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3,
         .CP0_LLAddr_rw_bitmask = 0,
@@ -147,7 +147,7 @@  static const mips_def_t mips_defs[] =
         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
                        (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
                        (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
-                       (1 << CP0C1_CA),
+                       (0 << CP0C1_CA),
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3,
         .CP0_LLAddr_rw_bitmask = 0,
@@ -188,7 +188,7 @@  static const mips_def_t mips_defs[] =
         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
                        (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
                        (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
-                       (1 << CP0C1_CA),
+                       (0 << CP0C1_CA),
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
         .CP0_LLAddr_rw_bitmask = 0,