From patchwork Mon Oct 26 09:46:42 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Juha.Riihimaki@nokia.com X-Patchwork-Id: 36892 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 15CB1B7BEB for ; Mon, 26 Oct 2009 20:48:02 +1100 (EST) Received: from localhost ([127.0.0.1]:56044 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1N2MBC-0001l2-L5 for incoming@patchwork.ozlabs.org; Mon, 26 Oct 2009 05:47:58 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1N2MAR-0001j2-Fi for qemu-devel@nongnu.org; Mon, 26 Oct 2009 05:47:11 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1N2MAK-0001ch-V2 for qemu-devel@nongnu.org; Mon, 26 Oct 2009 05:47:09 -0400 Received: from [199.232.76.173] (port=59118 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1N2MAK-0001ce-NJ for qemu-devel@nongnu.org; Mon, 26 Oct 2009 05:47:04 -0400 Received: from smtp.nokia.com ([192.100.105.134]:25073 helo=mgw-mx09.nokia.com) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1N2MAK-00069W-97 for qemu-devel@nongnu.org; Mon, 26 Oct 2009 05:47:04 -0400 Received: from esebh105.NOE.Nokia.com (esebh105.ntc.nokia.com [172.21.138.211]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id n9Q9kugN027371 for ; Mon, 26 Oct 2009 04:47:01 -0500 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by esebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 26 Oct 2009 11:46:43 +0200 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 26 Oct 2009 11:46:41 +0200 Received: from localhost.localdomain ([172.21.41.4]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id n9Q9kdip023300 for ; Mon, 26 Oct 2009 11:46:40 +0200 From: juha.riihimaki@nokia.com To: qemu-devel@nongnu.org Date: Mon, 26 Oct 2009 11:46:42 +0200 Message-Id: <1256550402-94129-1-git-send-email-juha.riihimaki@nokia.com> X-Mailer: git-send-email 1.6.5 MIME-Version: 1.0 X-OriginalArrivalTime: 26 Oct 2009 09:46:41.0577 (UTC) FILETIME=[38872190:01CA5621] X-Nokia-AV: Clean X-MIME-Autoconverted: from 8bit to quoted-printable by mgw-mx09.nokia.com id n9Q9kugN027371 X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6 (newer, 1) Subject: [Qemu-devel] [PATCH v3] target-arm: allow modifying vfp fpexc en bit only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Juha Riihimäki All other bits except for the EN in the VFP FPEXC register are defined as subarchitecture specific and real functionality for any of the other bits has not been implemented in QEMU. However, current code allows modifying all bits in the VFP FPEXC register leading to problems when guest code is writing 1's to the subarchitecture specific bits and checking whether the bits stay up to verify the existence of functionality which in fact does not exist in QEMU. This patch has been revised to include the same behavior change in the gdb register write function. Signed-off-by: Juha Riihimäki Acked-by: Laurent Desnogues --- target-arm/helper.c | 2 +- target-arm/translate.c | 3 +++ 2 files changed, 4 insertions(+), 1 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 701629a..ee5df59 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -233,7 +233,7 @@ static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg) switch (reg - nregs) { case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4; case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4; - case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf); return 4; + case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4; } return 0; } diff --git a/target-arm/translate.c b/target-arm/translate.c index 8503b92..d19ac7f 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -2804,6 +2804,9 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn) case ARM_VFP_FPEXC: if (IS_USER(s)) return 1; + /* TODO: VFP subarchitecture support. + * For now, keep the EN bit only */ + tcg_gen_andi_i32(tmp, tmp, 1 << 30); store_cpu_field(tmp, vfp.xregs[rn]); gen_lookup_tb(s); break;