From patchwork Sat Oct 24 12:19:02 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Juha.Riihimaki@nokia.com X-Patchwork-Id: 36832 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 1E085B7BCE for ; Sat, 24 Oct 2009 23:24:50 +1100 (EST) Received: from localhost ([127.0.0.1]:38514 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1N1ffr-00021V-2h for incoming@patchwork.ozlabs.org; Sat, 24 Oct 2009 08:24:47 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1N1fac-0008B5-HX for qemu-devel@nongnu.org; Sat, 24 Oct 2009 08:19:22 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1N1faX-00087d-Oo for qemu-devel@nongnu.org; Sat, 24 Oct 2009 08:19:21 -0400 Received: from [199.232.76.173] (port=58450 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1N1faX-00087Y-JW for qemu-devel@nongnu.org; Sat, 24 Oct 2009 08:19:17 -0400 Received: from smtp.nokia.com ([192.100.122.233]:52973 helo=mgw-mx06.nokia.com) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1N1faX-0004Gz-0t for qemu-devel@nongnu.org; Sat, 24 Oct 2009 08:19:17 -0400 Received: from esebh106.NOE.Nokia.com (esebh106.ntc.nokia.com [172.21.138.213]) by mgw-mx06.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id n9OCJEIA031308 for ; Sat, 24 Oct 2009 15:19:15 +0300 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by esebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Sat, 24 Oct 2009 15:19:13 +0300 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Sat, 24 Oct 2009 15:19:13 +0300 Received: from localhost.localdomain (essapo-nirac252105.europe.nokia.com [10.162.252.105]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id n9OCJ8q9022164 for ; Sat, 24 Oct 2009 15:19:12 +0300 From: juha.riihimaki@nokia.com To: qemu-devel@nongnu.org Date: Sat, 24 Oct 2009 15:19:02 +0300 Message-Id: <1256386749-85299-4-git-send-email-juha.riihimaki@nokia.com> X-Mailer: git-send-email 1.6.5 In-Reply-To: <1256386749-85299-1-git-send-email-juha.riihimaki@nokia.com> References: <1256386749-85299-1-git-send-email-juha.riihimaki@nokia.com> MIME-Version: 1.0 X-OriginalArrivalTime: 24 Oct 2009 12:19:13.0676 (UTC) FILETIME=[32C71CC0:01CA54A4] X-Nokia-AV: Clean X-MIME-Autoconverted: from 8bit to quoted-printable by mgw-mx06.nokia.com id n9OCJEIA031308 X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6 (newer, 1) Subject: [Qemu-devel] [PATCH v2 03/10] target-arm: allow modifying vfp fpexc en bit only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Juha Riihimäki All other bits except for the EN in the VFP FPEXC register are defined as subarchitecture specific and real functionality for any of the other bits has not been implemented in QEMU. However, current code allows modifying all bits in the VFP FPEXC register leading to problems when guest code is writing 1's to the subarchitecture specific bits and checking whether the bits stay up to verify the existence of functionality which in fact does not exist in QEMU. Signed-off-by: Juha Riihimäki --- target-arm/translate.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 09c996d..8cb1c0f 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -2788,6 +2788,9 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn) case ARM_VFP_FPEXC: if (IS_USER(s)) return 1; + /* TODO: VFP subarchitecture support. + * For now, keep the EN bit only */ + tcg_gen_andi_i32(tmp, tmp, 1 << 30); store_cpu_field(tmp, vfp.xregs[rn]); gen_lookup_tb(s); break;