@@ -203,12 +203,12 @@ static CPUReadMemoryFunc * const pci_apb_ioread[] = {
};
/* The APB host has an IRQ line for each IRQ line of each slot. */
-static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
+static int pci_apb_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
}
-static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
+static int pci_pbm_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
int bus_offset;
if (pci_dev->devfn & 1)
@@ -97,7 +97,7 @@ static CPUReadMemoryFunc * const pci_grackle_read[] = {
};
/* Don't know if this matches real hardware, but it agrees with OHW. */
-static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
+static int pci_grackle_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
return (irq_num + (pci_dev->devfn >> 3)) & 3;
}
@@ -866,7 +866,7 @@ static CPUReadMemoryFunc * const gt64120_read[] = {
>64120_readl,
};
-static int pci_gt64120_map_irq(PCIDevice *pci_dev, int irq_num)
+static int pci_gt64120_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
int slot;
@@ -294,7 +294,7 @@ static void ppc4xx_pci_reset(void *opaque)
/* On Bamboo, all pins from each slot are tied to a single board IRQ. This
* may need further refactoring for other boards. */
-static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
+static int ppc4xx_pci_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
int slot = pci_dev->devfn >> 3;
@@ -233,7 +233,7 @@ static CPUWriteMemoryFunc * const e500_pci_reg_write[] = {
&pci_reg_write4,
};
-static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
+static int mpc85xx_pci_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
int devno = pci_dev->devfn >> 3, ret = 0;
@@ -119,7 +119,7 @@ static CPUReadMemoryFunc * const PPC_PCIIO_read[] = {
&PPC_PCIIO_readl,
};
-static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
+static int prep_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
return (irq_num + (pci_dev->devfn >> 3)) & 1;
}
@@ -191,7 +191,7 @@ static void r2d_pci_set_irq(void *opaque, int n, int l)
qemu_set_irq(p[n], l);
}
-static int r2d_pci_map_irq(PCIDevice *d, int irq_num)
+static int r2d_pci_map_irq(void *opaque, PCIDevice *d, int irq_num)
{
const int intx[] = { PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD };
return intx[d->devfn >> 3];
@@ -136,7 +136,7 @@ static CPUReadMemoryFunc * const pci_unin_read[] = {
};
/* Don't know if this matches real hardware, but it agrees with OHW. */
-static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
+static int pci_unin_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
return (irq_num + (pci_dev->devfn >> 3)) & 3;
}
@@ -85,7 +85,7 @@ static CPUReadMemoryFunc * const pci_vpb_config_read[] = {
&pci_vpb_config_readl,
};
-static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
+static int pci_vpb_map_irq(void *opaque, PCIDevice *d, int irq_num)
{
return irq_num;
}
add opaque arg to pci_map_irq_fn. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> --- hw/apb_pci.c | 4 ++-- hw/grackle_pci.c | 2 +- hw/gt64xxx.c | 2 +- hw/ppc4xx_pci.c | 2 +- hw/ppce500_pci.c | 2 +- hw/prep_pci.c | 2 +- hw/r2d.c | 2 +- hw/unin_pci.c | 2 +- hw/versatile_pci.c | 2 +- 9 files changed, 10 insertions(+), 10 deletions(-)