From patchwork Thu Dec 11 02:20:23 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hu Tao X-Patchwork-Id: 419921 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id B770C140079 for ; Thu, 11 Dec 2014 13:24:41 +1100 (AEDT) Received: from localhost ([::1]:48774 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XytQk-0005t3-6D for incoming@patchwork.ozlabs.org; Wed, 10 Dec 2014 21:24:38 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51056) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XytQA-00051T-CR for qemu-devel@nongnu.org; Wed, 10 Dec 2014 21:24:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XytQ5-0004Uc-3E for qemu-devel@nongnu.org; Wed, 10 Dec 2014 21:24:02 -0500 Received: from [59.151.112.132] (port=32498 helo=heian.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XytQ4-0004Tu-O9 for qemu-devel@nongnu.org; Wed, 10 Dec 2014 21:23:57 -0500 X-IronPort-AV: E=Sophos;i="5.04,848,1406563200"; d="scan'208";a="44842763" Received: from unknown (HELO edo.cn.fujitsu.com) ([10.167.33.5]) by heian.cn.fujitsu.com with ESMTP; 11 Dec 2014 10:20:32 +0800 Received: from G08CNEXCHPEKD01.g08.fujitsu.local (localhost.localdomain [127.0.0.1]) by edo.cn.fujitsu.com (8.14.3/8.13.1) with ESMTP id sBB2NSmM025270; Thu, 11 Dec 2014 10:23:28 +0800 Received: from localhost.localdomain (10.167.226.102) by G08CNEXCHPEKD01.g08.fujitsu.local (10.167.33.89) with Microsoft SMTP Server (TLS) id 14.3.181.6; Thu, 11 Dec 2014 10:23:59 +0800 From: Hu Tao To: Date: Thu, 11 Dec 2014 10:20:23 +0800 Message-ID: <094404b0fbe3a2f7d49a3c30f4d128666b33b36b.1418264106.git.hutao@cn.fujitsu.com> X-Mailer: git-send-email 1.9.3 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.167.226.102] X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 59.151.112.132 Cc: Marcel Apfelbaum , "Michael S. Tsirkin" Subject: [Qemu-devel] [PATCH v3 1/6] pci: reorganize QEMU_PCI_CAP_* X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This makes code more readable. Signed-off-by: Hu Tao Reviewed-by: Marcel Apfelbaum --- include/hw/pci/pci.h | 39 ++++++++++++++++++++------------------- 1 file changed, 20 insertions(+), 19 deletions(-) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index c352c7b..b18759a 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -142,25 +142,26 @@ enum { /* Bits in cap_present field. */ enum { - QEMU_PCI_CAP_MSI = 0x1, - QEMU_PCI_CAP_MSIX = 0x2, - QEMU_PCI_CAP_EXPRESS = 0x4, - - /* multifunction capable device */ -#define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 - QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), - - /* command register SERR bit enabled */ -#define QEMU_PCI_CAP_SERR_BITNR 4 - QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), - /* Standard hot plug controller. */ -#define QEMU_PCI_SHPC_BITNR 5 - QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), -#define QEMU_PCI_SLOTID_BITNR 6 - QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), - /* PCI Express capability - Power Controller Present */ -#define QEMU_PCIE_SLTCAP_PCP_BITNR 7 - QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), + QEMU_PCI_CAP_MSI_BITNR = 0, + QEMU_PCI_CAP_MSIX_BITNR, + QEMU_PCI_CAP_EXPRESS_BITNR, + QEMU_PCI_CAP_MULTIFUNCTION_BITNR, /* multifunction capable device */ + QEMU_PCI_CAP_SERR_BITNR, /* command register SERR bit enabled */ + QEMU_PCI_SHPC_BITNR, /* Standard hot plug controller */ + QEMU_PCI_SLOTID_BITNR, + QEMU_PCIE_SLTCAP_PCP_BITNR, /* PCI Express capability - Power Controller + Present */ +}; + +enum { + QEMU_PCI_CAP_MSI = (1 << QEMU_PCI_CAP_MSI_BITNR), + QEMU_PCI_CAP_MSIX = (1 << QEMU_PCI_CAP_MSIX_BITNR), + QEMU_PCI_CAP_EXPRESS = (1 << QEMU_PCI_CAP_EXPRESS_BITNR), + QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), + QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), + QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), + QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), + QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), }; #define TYPE_PCI_DEVICE "pci-device"