Show patches with: Submitter = Palmer Dabbelt       |    State = Action Required       |    Archived = No       |   65 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[PULL,6/6] riscv/sifive_u: Add a serial property to the sifive_u machine [PULL,1/6] target/riscv: Don't set write permissions on dirty PTEs - - 2 - --- 2020-04-21 Palmer Dabbelt New
[PULL,5/6] riscv/sifive_u: Add a serial property to the sifive_u SoC [PULL,1/6] target/riscv: Don't set write permissions on dirty PTEs - - 1 1 --- 2020-04-21 Palmer Dabbelt New
[PULL,4/6] riscv/sifive_u: Fix up file ordering [PULL,1/6] target/riscv: Don't set write permissions on dirty PTEs - - 1 - --- 2020-04-21 Palmer Dabbelt New
[PULL,3/6] riscv: AND stage-1 and stage-2 protection flags [PULL,1/6] target/riscv: Don't set write permissions on dirty PTEs - - 1 - --- 2020-04-21 Palmer Dabbelt New
[PULL,2/6] riscv: Don't use stage-2 PTE lookup protection flags [PULL,1/6] target/riscv: Don't set write permissions on dirty PTEs - - 1 - --- 2020-04-21 Palmer Dabbelt New
[PULL,1/6] target/riscv: Don't set write permissions on dirty PTEs [PULL,1/6] target/riscv: Don't set write permissions on dirty PTEs - - 1 - --- 2020-04-21 Palmer Dabbelt New
[PULL] RISC-V Patches for 5.0-rc4 [PULL] RISC-V Patches for 5.0-rc4 - - - - --- 2020-04-21 Palmer Dabbelt New
[PULL,6/6] target/riscv: Fix VS mode interrupts forwarding. [PULL,1/6] target/riscv: Correctly implement TSR trap - - 1 - --- 2020-03-17 Palmer Dabbelt New
[PULL,5/6] gitlab-ci.yml: Add jobs to build OpenSBI firmware binaries [PULL,1/6] target/riscv: Correctly implement TSR trap - - - - --- 2020-03-17 Palmer Dabbelt New
[PULL,4/6] riscv: sifive_u: Update BIOS_FILENAME for 32-bit [PULL,1/6] target/riscv: Correctly implement TSR trap - - 1 - --- 2020-03-17 Palmer Dabbelt New
[PULL,3/6] roms: opensbi: Add 32-bit firmware image for sifive_u machine [PULL,1/6] target/riscv: Correctly implement TSR trap - - 1 - --- 2020-03-17 Palmer Dabbelt New
[PULL,2/6] roms: opensbi: Upgrade from v0.5 to v0.6 [PULL,1/6] target/riscv: Correctly implement TSR trap - - 1 - --- 2020-03-17 Palmer Dabbelt New
[PULL,1/6] target/riscv: Correctly implement TSR trap [PULL,1/6] target/riscv: Correctly implement TSR trap - - 1 - --- 2020-03-17 Palmer Dabbelt New
[PULL] RISC-V: Add a missing "," in riscv_excp_names [PULL] RISC-V: Add a missing "," in riscv_excp_names - 1 1 - --- 2020-03-05 Palmer Dabbelt New
RISC-V: Add a missing "," in riscv_excp_names RISC-V: Add a missing "," in riscv_excp_names - 1 1 - --- 2020-03-05 Palmer Dabbelt New
[PULL,38/38] hw/riscv: Provide rdtime callback for TCG in CLINT emulation [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,37/38] target/riscv: Emulate TIME CSRs for privileged mode [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,36/38] riscv: virt: Allow PCI address 0 [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,35/38] target/riscv: Allow enabling the Hypervisor extension [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,34/38] target/riscv: Add the MSTATUS_MPV_ISSET helper macro [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,33/38] target/riscv: Add support for the 32-bit MSTATUSH CSR [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,32/38] target/riscv: Set htval and mtval2 on execptions [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,31/38] target/riscv: Raise the new execptions when 2nd stage translation fails [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,30/38] target/riscv: Implement second stage MMU [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,29/38] target/riscv: Allow specifying MMU stage [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,28/38] target/riscv: Respect MPRV and SPRV for floating point ops [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,27/38] target/riscv: Mark both sstatus and msstatus_hs as dirty [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,26/38] target/riscv: Disable guest FP support based on virtual status [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,25/38] target/riscv: Only set TB flags with FP status if enabled [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,24/38] target/riscv: Remove the hret instruction [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,23/38] target/riscv: Add hfence instructions [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,22/38] target/riscv: Add Hypervisor trap return support [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,21/38] target/riscv: Add hypvervisor trap support [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,20/38] target/riscv: Generate illegal instruction on WFI when V=1 [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,19/38] target/ricsv: Flush the TLB on virtulisation mode changes [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,18/38] target/riscv: Add support for virtual interrupt setting [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,17/38] target/riscv: Extend the SIP CSR to support virtulisation [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,16/38] target/riscv: Extend the MIE CSR to support virtulisation [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,15/38] target/riscv: Set VS bits in mideleg for Hyp extension [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,14/38] target/riscv: Add virtual register swapping function [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,13/38] target/riscv: Add Hypervisor machine CSRs accesses [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,12/38] target/riscv: Add Hypervisor virtual CSRs accesses [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,11/38] target/riscv: Add Hypervisor CSR access functions [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,10/38] target/riscv: Dump Hypervisor registers if enabled [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,09/38] target/riscv: Print priv and virt in disas log [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,08/38] target/riscv: Fix CSR perm checking for HS mode [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,07/38] target/riscv: Add the force HS exception mode [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,06/38] target/riscv: Add the virtulisation mode [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,05/38] target/riscv: Rename the H irqs to VS irqs [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,04/38] target/riscv: Add support for the new execption numbers [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,03/38] target/riscv: Add the Hypervisor CSRs to CPUState [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,02/38] target/riscv: Add the Hypervisor extension [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 2 - --- 2020-03-03 Palmer Dabbelt New
[PULL,01/38] target/riscv: Convert MIP CSR to target_ulong [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,5/5] MAINTAINERS: Add maintainer entry for Goldfish RTC [PULL,1/5] riscv/virt: Add syscon reboot and poweroff DT nodes - - 1 - --- 2020-02-12 Palmer Dabbelt New
[PULL,4/5] riscv: virt: Use Goldfish RTC device [PULL,1/5] riscv/virt: Add syscon reboot and poweroff DT nodes 1 - 2 - --- 2020-02-12 Palmer Dabbelt New
[PULL,3/5] hw: rtc: Add Goldfish RTC device [PULL,1/5] riscv/virt: Add syscon reboot and poweroff DT nodes - - 1 - --- 2020-02-12 Palmer Dabbelt New
[PULL,2/5] riscv: Separate FPU register size from core register size in gdbstub [v2] [PULL,1/5] riscv/virt: Add syscon reboot and poweroff DT nodes - - - - --- 2020-02-12 Palmer Dabbelt New
[PULL,1/5] riscv/virt: Add syscon reboot and poweroff DT nodes [PULL,1/5] riscv/virt: Add syscon reboot and poweroff DT nodes - - 1 - --- 2020-02-12 Palmer Dabbelt New
[PULL,5/5] target/riscv: update mstatus.SD when FS is set dirty [PULL,1/5] riscv/sifive_u: fix a memory leak in soc_realize() - - 2 - --- 2020-01-21 Palmer Dabbelt New
[PULL,4/5] target/riscv: fsd/fsw doesn't dirty FP state [PULL,1/5] riscv/sifive_u: fix a memory leak in soc_realize() - - 2 - --- 2020-01-21 Palmer Dabbelt New
[PULL,3/5] target/riscv: Fix tb->flags FS status [PULL,1/5] riscv/sifive_u: fix a memory leak in soc_realize() - - 1 - --- 2020-01-21 Palmer Dabbelt New
[PULL,2/5] riscv: Set xPIE to 1 after xRET [PULL,1/5] riscv/sifive_u: fix a memory leak in soc_realize() - - 2 1 --- 2020-01-21 Palmer Dabbelt New
[PULL,1/5] riscv/sifive_u: fix a memory leak in soc_realize() [PULL,1/5] riscv/sifive_u: fix a memory leak in soc_realize() - - 2 - --- 2020-01-21 Palmer Dabbelt New
[PULL,2/2] hw/riscv: Add optional symbol callback ptr to riscv_load_kernel() [PULL,1/2] RISC-V: virt: This is a "sifive,test1" test finisher - 1 1 - --- 2019-11-25 Palmer Dabbelt New
[PULL,1/2] RISC-V: virt: This is a "sifive,test1" test finisher [PULL,1/2] RISC-V: virt: This is a "sifive,test1" test finisher - 1 1 - --- 2019-11-25 Palmer Dabbelt New