Show patches with: Submitter = Alistair Francis       |    State = Action Required       |    Archived = No       |   1748 patches
« 1 2 3 4 … 17 18 »
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[PULL,24/42] target/riscv: Implementation of enhanced PMP (ePMP) [PULL,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 1 - --- 2021-05-03 Alistair Francis New
[PULL,23/42] target/riscv: Add ePMP CSR access functions [PULL,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 2 - --- 2021-05-03 Alistair Francis New
[PULL,22/42] target/riscv: Add the ePMP feature [PULL,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 1 - --- 2021-05-03 Alistair Francis New
[PULL,21/42] target/riscv: Define ePMP mseccfg [PULL,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 3 - --- 2021-05-03 Alistair Francis New
[PULL,20/42] target/riscv: Fix the PMP is locked check when using TOR [PULL,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 1 - --- 2021-05-03 Alistair Francis New
[PULL,19/42] docs: Add documentation for shakti_c machine [PULL,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 1 - --- 2021-05-03 Alistair Francis New
[PULL,18/42] target/riscv: Fixup saturate subtract function [PULL,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 2 - --- 2021-05-03 Alistair Francis New
[PULL,17/42] riscv: don't look at SUM when accessing memory from a debugger context [PULL,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 1 - --- 2021-05-03 Alistair Francis New
[PULL,16/42] hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine [PULL,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 1 - --- 2021-05-03 Alistair Francis New
[PULL,15/42] hw/opentitan: Update the interrupt layout [PULL,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 1 - --- 2021-05-03 Alistair Francis New
[PULL,14/42] MAINTAINERS: Update the RISC-V CPU Maintainers [PULL,01/42] target/riscv: Remove privilege v1.9 specific CSR related code 2 - 1 - --- 2021-05-03 Alistair Francis New
[PULL,13/42] target/riscv: Use RISCVException enum for CSR access [PULL,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 2 - --- 2021-05-03 Alistair Francis New
[PULL,12/42] target/riscv: Use the RISCVException enum for CSR operations [PULL,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 2 - --- 2021-05-03 Alistair Francis New
[PULL,11/42] target/riscv: Fix 32-bit HS mode access permissions [PULL,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 2 - --- 2021-05-03 Alistair Francis New
[PULL,10/42] target/riscv: Use the RISCVException enum for CSR predicates [PULL,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 2 - --- 2021-05-03 Alistair Francis New
[PULL,09/42] target/riscv: Convert the RISC-V exceptions to an enum [PULL,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 2 - --- 2021-05-03 Alistair Francis New
[PULL,08/42] hw/riscv: Connect Shakti UART to Shakti platform [PULL,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 1 - --- 2021-05-03 Alistair Francis New
[PULL,07/42] hw/char: Add Shakti UART emulation [PULL,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 1 - --- 2021-05-03 Alistair Francis New
[PULL,06/42] riscv: Add initial support for Shakti C machine [PULL,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 1 - --- 2021-05-03 Alistair Francis New
[PULL,05/42] target/riscv: Add Shakti C class CPU [PULL,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 1 - --- 2021-05-03 Alistair Francis New
[PULL,04/42] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[] [PULL,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - 1 2 - --- 2021-05-03 Alistair Francis New
[PULL,03/42] target/riscv: Align the data type of reset vector address [PULL,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 2 - --- 2021-05-03 Alistair Francis New
[PULL,02/42] docs/system/generic-loader.rst: Fix style [PULL,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 1 - --- 2021-05-03 Alistair Francis New
[PULL,01/42] target/riscv: Remove privilege v1.9 specific CSR related code [PULL,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 1 - --- 2021-05-03 Alistair Francis New
[PULL,00/42] riscv-to-apply queue - - - - --- 2021-05-03 Alistair Francis New
[v3,10/10] target/riscv: Fix the RV64H decode comment RISC-V: Steps towards running 32-bit guests on - - 1 - --- 2021-04-24 Alistair Francis New
[v3,09/10] target/riscv: Consolidate RV32/64 16-bit instructions RISC-V: Steps towards running 32-bit guests on - - 1 - --- 2021-04-24 Alistair Francis New
[v3,08/10] target/riscv: Consolidate RV32/64 32-bit instructions RISC-V: Steps towards running 32-bit guests on - - 1 - --- 2021-04-24 Alistair Francis New
[v3,07/10] target/riscv: Remove an unused CASE_OP_32_64 macro RISC-V: Steps towards running 32-bit guests on - - 2 - --- 2021-04-24 Alistair Francis New
[v3,06/10] target/riscv: Remove the unused HSTATUS_WPRI macro RISC-V: Steps towards running 32-bit guests on - - 2 - --- 2021-04-24 Alistair Francis New
[v3,05/10] target/riscv: Remove the hardcoded SATP_MODE macro RISC-V: Steps towards running 32-bit guests on - - 1 - --- 2021-04-24 Alistair Francis New
[v3,04/10] target/riscv: Remove the hardcoded MSTATUS_SD macro RISC-V: Steps towards running 32-bit guests on - - 1 - --- 2021-04-24 Alistair Francis New
[v3,03/10] target/riscv: Remove the hardcoded HGATP_MODE macro RISC-V: Steps towards running 32-bit guests on - - 2 - --- 2021-04-24 Alistair Francis New
[v3,02/10] target/riscv: Remove the hardcoded SSTATUS_SD macro RISC-V: Steps towards running 32-bit guests on - - 2 - --- 2021-04-24 Alistair Francis New
[v3,01/10] target/riscv: Remove the hardcoded RVXLEN macro RISC-V: Steps towards running 32-bit guests on - - 2 - --- 2021-04-24 Alistair Francis New
[v4,8/8] target/riscv: Add ePMP support for the Ibex CPU RISC-V: Add support for ePMP v0.9.1 - - 1 - --- 2021-04-19 Alistair Francis New
[v4,7/8] target/riscv/pmp: Remove outdated comment RISC-V: Add support for ePMP v0.9.1 - - 1 - --- 2021-04-19 Alistair Francis New
[v4,6/8] target/riscv: Add a config option for ePMP RISC-V: Add support for ePMP v0.9.1 - - 1 - --- 2021-04-19 Alistair Francis New
[v4,5/8] target/riscv: Implementation of enhanced PMP (ePMP) RISC-V: Add support for ePMP v0.9.1 - - 1 - --- 2021-04-19 Alistair Francis New
[v4,4/8] target/riscv: Add ePMP CSR access functions RISC-V: Add support for ePMP v0.9.1 - - 1 - --- 2021-04-19 Alistair Francis New
[v4,3/8] target/riscv: Add the ePMP feature RISC-V: Add support for ePMP v0.9.1 - - 1 - --- 2021-04-19 Alistair Francis New
[v4,2/8] target/riscv: Define ePMP mseccfg RISC-V: Add support for ePMP v0.9.1 - - 2 - --- 2021-04-19 Alistair Francis New
[v4,1/8] target/riscv: Fix the PMP is locked check when using TOR RISC-V: Add support for ePMP v0.9.1 - - 1 - --- 2021-04-19 Alistair Francis New
[v2,9/9] target/riscv: Consolidate RV32/64 16-bit instructions RISC-V: Steps towards running 32-bit guests on - - 1 - --- 2021-04-13 Alistair Francis New
[v2,8/9] target/riscv: Consolidate RV32/64 32-bit instructions RISC-V: Steps towards running 32-bit guests on - - - - --- 2021-04-13 Alistair Francis New
[v2,7/9] target/riscv: Remove an unused CASE_OP_32_64 macro RISC-V: Steps towards running 32-bit guests on - - 2 - --- 2021-04-13 Alistair Francis New
[v2,6/9] target/riscv: Remove the unused HSTATUS_WPRI macro RISC-V: Steps towards running 32-bit guests on - - 2 - --- 2021-04-13 Alistair Francis New
[v2,5/9] target/riscv: Remove the hardcoded SATP_MODE macro RISC-V: Steps towards running 32-bit guests on - - 1 - --- 2021-04-13 Alistair Francis New
[v2,4/9] target/riscv: Remove the hardcoded MSTATUS_SD macro RISC-V: Steps towards running 32-bit guests on - - 1 - --- 2021-04-13 Alistair Francis New
[v2,3/9] target/riscv: Remove the hardcoded HGATP_MODE macro RISC-V: Steps towards running 32-bit guests on - - 2 - --- 2021-04-13 Alistair Francis New
[v2,2/9] target/riscv: Remove the hardcoded SSTATUS_SD macro RISC-V: Steps towards running 32-bit guests on - - 2 - --- 2021-04-13 Alistair Francis New
[v2,1/9] target/riscv: Remove the hardcoded RVXLEN macro RISC-V: Steps towards running 32-bit guests on - - 2 - --- 2021-04-13 Alistair Francis New
[v3,8/8] target/riscv: Add ePMP support for the Ibex CPU RISC-V: Add support for ePMP v0.9.1 - - 1 - --- 2021-04-13 Alistair Francis New
[v3,7/8] target/riscv/pmp: Remove outdated comment RISC-V: Add support for ePMP v0.9.1 - - 1 - --- 2021-04-13 Alistair Francis New
[v3,6/8] target/riscv: Add a config option for ePMP RISC-V: Add support for ePMP v0.9.1 - - 1 - --- 2021-04-13 Alistair Francis New
[v3,5/8] target/riscv: Implementation of enhanced PMP (ePMP) RISC-V: Add support for ePMP v0.9.1 - - - - --- 2021-04-13 Alistair Francis New
[v3,4/8] target/riscv: Add ePMP CSR access functions RISC-V: Add support for ePMP v0.9.1 - - 1 - --- 2021-04-13 Alistair Francis New
[v3,3/8] target/riscv: Add the ePMP feature RISC-V: Add support for ePMP v0.9.1 - - 1 - --- 2021-04-13 Alistair Francis New
[v3,2/8] target/riscv: Define ePMP mseccfg RISC-V: Add support for ePMP v0.9.1 - - 2 - --- 2021-04-13 Alistair Francis New
[v3,1/8] target/riscv: Fix the PMP is locked check when using TOR RISC-V: Add support for ePMP v0.9.1 - - 1 - --- 2021-04-13 Alistair Francis New
[v2,8/8] target/riscv: Add ePMP support for the Ibex CPU RISC-V: Add support for ePMP v0.9.1 - - 1 - --- 2021-04-09 Alistair Francis New
[v2,7/8] target/riscv/pmp: Remove outdated comment RISC-V: Add support for ePMP v0.9.1 - - 1 - --- 2021-04-09 Alistair Francis New
[v2,6/8] target/riscv: Add a config option for ePMP RISC-V: Add support for ePMP v0.9.1 - - 1 - --- 2021-04-09 Alistair Francis New
[v2,5/8] target/riscv: Implementation of enhanced PMP (ePMP) RISC-V: Add support for ePMP v0.9.1 - - - - --- 2021-04-09 Alistair Francis New
[v2,4/8] target/riscv: Add ePMP CSR access functions RISC-V: Add support for ePMP v0.9.1 - - 1 - --- 2021-04-09 Alistair Francis New
[v2,3/8] target/riscv: Add the ePMP feature RISC-V: Add support for ePMP v0.9.1 - - 1 - --- 2021-04-09 Alistair Francis New
[v2,2/8] target/riscv: Define ePMP mseccfg RISC-V: Add support for ePMP v0.9.1 - - 2 - --- 2021-04-09 Alistair Francis New
[v2,1/8] target/riscv: Fix the PMP is locked check when using TOR RISC-V: Add support for ePMP v0.9.1 - - 1 - --- 2021-04-09 Alistair Francis New
[v1,1/1] MAINTAINERS: Update the RISC-V CPU Maintainers [v1,1/1] MAINTAINERS: Update the RISC-V CPU Maintainers 2 - 1 - --- 2021-04-06 Alistair Francis New
[v1,8/8] target/riscv: Include RV32 instructions in RV64 build RISC-V: Steps towards running 32-bit guests on - - - - --- 2021-04-02 Alistair Francis New
[v1,7/8] target/riscv: Remove an unused CASE_OP_32_64 macro RISC-V: Steps towards running 32-bit guests on - - 2 - --- 2021-04-02 Alistair Francis New
[v1,6/8] target/riscv: Remove the unused HSTATUS_WPRI macro RISC-V: Steps towards running 32-bit guests on - - 2 - --- 2021-04-02 Alistair Francis New
[v1,5/8] target/riscv: Remove the hardcoded SATP_MODE macro RISC-V: Steps towards running 32-bit guests on - - - - --- 2021-04-02 Alistair Francis New
[v1,4/8] target/riscv: Remove the hardcoded MSTATUS_SD macro RISC-V: Steps towards running 32-bit guests on - - - - --- 2021-04-02 Alistair Francis New
[v1,3/8] target/riscv: Remove the hardcoded HGATP_MODE macro RISC-V: Steps towards running 32-bit guests on - - 1 - --- 2021-04-02 Alistair Francis New
[v1,2/8] target/riscv: Remove the hardcoded SSTATUS_SD macro RISC-V: Steps towards running 32-bit guests on - - 2 - --- 2021-04-02 Alistair Francis New
[v1,1/8] target/riscv: Remove the hardcoded RVXLEN macro RISC-V: Steps towards running 32-bit guests on - - 2 - --- 2021-04-02 Alistair Francis New
[v1,8/8] target/riscv: Add ePMP support for the Ibex CPU RISC-V: Add support for ePMP v0.9.1 - - 1 - --- 2021-04-02 Alistair Francis New
[v1,7/8] target/riscv/pmp: Remove outdated comment RISC-V: Add support for ePMP v0.9.1 - - 1 - --- 2021-04-02 Alistair Francis New
[v1,6/8] target/riscv: Add a config option for ePMP RISC-V: Add support for ePMP v0.9.1 - - 1 - --- 2021-04-02 Alistair Francis New
[v1,5/8] target/riscv: Implementation of enhanced PMP (ePMP) RISC-V: Add support for ePMP v0.9.1 - - - - --- 2021-04-02 Alistair Francis New
[v1,4/8] target/riscv: Add ePMP CSR access functions RISC-V: Add support for ePMP v0.9.1 - - 1 - --- 2021-04-02 Alistair Francis New
[v1,3/8] target/riscv: Add the ePMP feature RISC-V: Add support for ePMP v0.9.1 - - 1 - --- 2021-04-02 Alistair Francis New
[v1,2/8] target/riscv: Define ePMP mseccfg RISC-V: Add support for ePMP v0.9.1 - - 2 - --- 2021-04-02 Alistair Francis New
[v1,1/8] target/riscv: Fix the PMP is locked check when using TOR RISC-V: Add support for ePMP v0.9.1 - - 1 - --- 2021-04-02 Alistair Francis New
[v1,2/2] sifive_u: Connect the SiFive PWM device Add the SiFive PWM device - - - - --- 2021-04-02 Alistair Francis New
[v1,1/2] sifive_u_pwm: Initial commit Add the SiFive PWM device - - - - --- 2021-04-02 Alistair Francis New
[v1,1/1] hw/riscv: Enalbe VIRTIO_VGA for RISC-V virt machine [v1,1/1] hw/riscv: Enalbe VIRTIO_VGA for RISC-V virt machine - - 1 - --- 2021-04-02 Alistair Francis New
[v2,5/5] target/riscv: Use RISCVException enum for CSR access RISC-V: Convert the CSR access functions to use - - 2 - --- 2021-04-01 Alistair Francis New
[v2,4/5] target/riscv: Use the RISCVException enum for CSR operations RISC-V: Convert the CSR access functions to use - - 2 - --- 2021-04-01 Alistair Francis New
[v2,3/5] target/riscv: Fix 32-bit HS mode access permissions RISC-V: Convert the CSR access functions to use - - 2 - --- 2021-04-01 Alistair Francis New
[v2,2/5] target/riscv: Use the RISCVException enum for CSR predicates RISC-V: Convert the CSR access functions to use - - 2 - --- 2021-04-01 Alistair Francis New
[v2,1/5] target/riscv: Convert the RISC-V exceptions to an enum RISC-V: Convert the CSR access functions to use - - 2 - --- 2021-04-01 Alistair Francis New
[v1,1/1] hw/opentitan: Update the interrupt layout [v1,1/1] hw/opentitan: Update the interrupt layout - - 1 - --- 2021-03-31 Alistair Francis New
[PULL,16/16] target/riscv: Prevent lost illegal instruction exceptions [PULL,01/16] target/riscv: fix vs() to return proper error code - - 2 - --- 2021-03-23 Alistair Francis New
[PULL,15/16] docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine [PULL,01/16] target/riscv: fix vs() to return proper error code - - 1 - --- 2021-03-23 Alistair Francis New
[PULL,14/16] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register [PULL,01/16] target/riscv: fix vs() to return proper error code - - 1 - --- 2021-03-23 Alistair Francis New
[PULL,13/16] hw/block: m25p80: Support fast read for SST flashes [PULL,01/16] target/riscv: fix vs() to return proper error code 1 - - - --- 2021-03-23 Alistair Francis New
[PULL,12/16] target/riscv: Add proper two-stage lookup exception detection [PULL,01/16] target/riscv: fix vs() to return proper error code - - 1 - --- 2021-03-23 Alistair Francis New
[PULL,11/16] target/riscv: Fix read and write accesses to vsip and vsie [PULL,01/16] target/riscv: fix vs() to return proper error code - - 1 - --- 2021-03-23 Alistair Francis New
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