Show patches with: Submitter = Alistair Francis       |    State = Action Required       |   1748 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[PULL,v4,2/7] hw/riscv/sifive_e: Create a SiFive E SoC object riscv-pull queue - - 1 - --- 2018-07-06 Alistair Francis New
[PULL,v4,1/7] hw/riscv/sifive_u: Create a SiFive U SoC object riscv-pull queue - - 1 - --- 2018-07-06 Alistair Francis New
[PULL,v3,7/7] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device riscv-pull queue - - 1 - --- 2018-07-03 Alistair Francis New
[PULL,v3,6/7] hw/riscv/sifive_u: Move the uart device tree node under /soc/ riscv-pull queue - - 1 - --- 2018-07-03 Alistair Francis New
[PULL,v3,5/7] hw/riscv/sifive_u: Set the interrupt controler number of interrupts riscv-pull queue - - 1 - --- 2018-07-03 Alistair Francis New
[PULL,v3,4/7] hw/riscv/sifive_u: Set the soc device tree node as a simple-bus riscv-pull queue - - 1 - --- 2018-07-03 Alistair Francis New
[PULL,v3,3/7] hw/riscv/sifive_plic: Use gpios instead of irqs riscv-pull queue - - 2 - --- 2018-07-03 Alistair Francis New
[PULL,v3,2/7] hw/riscv/sifive_e: Create a SiFive E SoC object riscv-pull queue - - 1 - --- 2018-07-03 Alistair Francis New
[PULL,v3,1/7] hw/riscv/sifive_u: Create a SiFive U SoC object riscv-pull queue - - 1 - --- 2018-07-03 Alistair Francis New
[PULL,v2,7/7] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device riscv-pull queue - - 1 - --- 2018-06-29 Alistair Francis New
[PULL,v2,6/7] hw/riscv/sifive_u: Move the uart device tree node under /soc/ riscv-pull queue - - 1 - --- 2018-06-29 Alistair Francis New
[PULL,v2,5/7] hw/riscv/sifive_u: Set the interrupt controler number of interrupts riscv-pull queue - - 1 - --- 2018-06-29 Alistair Francis New
[PULL,v2,4/7] hw/riscv/sifive_u: Set the soc device tree node as a simple-bus riscv-pull queue - - 1 - --- 2018-06-29 Alistair Francis New
[PULL,v2,3/7] hw/riscv/sifive_plic: Use gpios instead of irqs riscv-pull queue - - 2 - --- 2018-06-29 Alistair Francis New
[PULL,v2,2/7] hw/riscv/sifive_e: Create a SiFive E SoC object riscv-pull queue - - 1 - --- 2018-06-29 Alistair Francis New
[PULL,v2,1/7] hw/riscv/sifive_u: Create a SiFive U SoC object riscv-pull queue - - 1 - --- 2018-06-29 Alistair Francis New
[PULL,7/7] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device riscv-pull queue - - 1 - --- 2018-06-27 Alistair Francis New
[PULL,6/7] hw/riscv/sifive_u: Move the uart device tree node under /soc/ riscv-pull queue - - 1 - --- 2018-06-27 Alistair Francis New
[PULL,5/7] hw/riscv/sifive_u: Set the interrupt controler number of interrupts riscv-pull queue - - 1 - --- 2018-06-27 Alistair Francis New
[PULL,4/7] hw/riscv/sifive_u: Set the soc device tree node as a simple-bus riscv-pull queue - - 1 - --- 2018-06-27 Alistair Francis New
[PULL,3/7] hw/riscv/sifive_plic: Use gpios instead of irqs riscv-pull queue - - 2 - --- 2018-06-27 Alistair Francis New
[PULL,2/7] hw/riscv/sifive_e: Create a SiFive E SoC object riscv-pull queue - - 1 - --- 2018-06-27 Alistair Francis New
[PULL,1/7] hw/riscv/sifive_u: Create a SiFive U SoC object riscv-pull queue - - 1 - --- 2018-06-27 Alistair Francis New
[v1,5/5] riscv64-softmmu.mak: Build Virtio Block support Connect a PCIe host and graphics support to RISC-V - - - - --- 2018-06-22 Alistair Francis New
[v1,4/5] hw/riscv/virt: Connect a VGA PCIe device Connect a PCIe host and graphics support to RISC-V - - - - --- 2018-06-22 Alistair Francis New
[v1,3/5] hw/riscv/virt: Connect the Xilinx PCIe Connect a PCIe host and graphics support to RISC-V - - - - --- 2018-06-22 Alistair Francis New
[v1,2/5] hw/riscv/virt: Increase the number of interrupts Connect a PCIe host and graphics support to RISC-V - - - - --- 2018-06-22 Alistair Francis New
[v1,1/5] hw/riscv/virtio: Set the soc device tree node as a simple-bus Connect a PCIe host and graphics support to RISC-V - - - - --- 2018-06-22 Alistair Francis New
[v2,1/1] tests/docker: Add a Avocado Docker test [v2,1/1] tests/docker: Add a Avocado Docker test - - 1 - --- 2018-05-18 Alistair Francis New
[v3,7/7] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device RISC-V: SoCify SiFive boards and connect GEM - - 1 - --- 2018-05-15 Alistair Francis New
[v3,6/7] hw/riscv/sifive_u: Move the uart device tree node under /soc/ RISC-V: SoCify SiFive boards and connect GEM - - 1 - --- 2018-05-15 Alistair Francis New
[v3,5/7] hw/riscv/sifive_u: Set the interrupt controler number of interrupts RISC-V: SoCify SiFive boards and connect GEM - - 1 - --- 2018-05-15 Alistair Francis New
[v3,4/7] hw/riscv/sifive_u: Set the soc device tree node as a simple-bus RISC-V: SoCify SiFive boards and connect GEM - - 1 - --- 2018-05-15 Alistair Francis New
[v3,3/7] hw/riscv/sifive_plic: Use gpios instead of irqs RISC-V: SoCify SiFive boards and connect GEM - - 2 - --- 2018-05-15 Alistair Francis New
[v3,2/7] hw/riscv/sifive_e: Create a SiFive E SoC object RISC-V: SoCify SiFive boards and connect GEM - - 1 - --- 2018-05-15 Alistair Francis New
[v3,1/7] hw/riscv/sifive_u: Create a SiFive U SoC object RISC-V: SoCify SiFive boards and connect GEM - - 1 - --- 2018-05-15 Alistair Francis New
[v2,7/7] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device RISC-V: SoCify SiFive boards and connect GEM - - 1 - --- 2018-05-11 Alistair Francis New
[v2,6/7] hw/riscv/sifive_u: Move the uart device tree node under /soc/ RISC-V: SoCify SiFive boards and connect GEM - - 1 - --- 2018-05-11 Alistair Francis New
[v2,5/7] hw/riscv/sifive_u: Set the interrupt controler number of interrupts RISC-V: SoCify SiFive boards and connect GEM - - 1 - --- 2018-05-11 Alistair Francis New
[v2,4/7] hw/riscv/sifive_u: Set the soc device tree node as a simple-bus RISC-V: SoCify SiFive boards and connect GEM - - - - --- 2018-05-11 Alistair Francis New
[v2,3/7] hw/riscv/sifive_plic: Use gpios instead of irqs RISC-V: SoCify SiFive boards and connect GEM - - - - --- 2018-05-11 Alistair Francis New
[v2,2/7] hw/riscv/sifive_e: Create a E31 SoC object RISC-V: SoCify SiFive boards and connect GEM - - - - --- 2018-05-11 Alistair Francis New
[v2,1/7] hw/riscv/sifive_u: Create a U54 SoC object RISC-V: SoCify SiFive boards and connect GEM - - 1 - --- 2018-05-11 Alistair Francis New
[v1,1/1] tests/docker: Add a Avocado Docker test [v1,1/1] tests/docker: Add a Avocado Docker test - - - - --- 2018-05-07 Alistair Francis New
[v1,4/4] hw/riscv/sifive_e: Create a E31 SoC object RISC-V: SoCify the SiFive boards and connect the - - - - --- 2018-05-04 Alistair Francis New
[v1,3/4] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device RISC-V: SoCify the SiFive boards and connect the - - - - --- 2018-05-04 Alistair Francis New
[v1,2/4] hw/riscv/sifive_plic: Use gpios instead of irqs RISC-V: SoCify the SiFive boards and connect the - - - - --- 2018-05-04 Alistair Francis New
[v1,1/4] hw/riscv/sifive_u: Create a U54 SoC object RISC-V: SoCify the SiFive boards and connect the - - - - --- 2018-05-04 Alistair Francis New
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