Show patches with: Submitter = Bin Meng       |    State = Action Required       |    Archived = No       |   300 patches
« 1 2 3 »
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v6,6/6] gitlab-ci/opensbi: Update GitLab CI to build generic platform riscv: Switch to use generic platform fw_dynamic type opensbi bios images - - 2 - --- 2020-08-03 Bin Meng New
[v6,5/6] hw/riscv: spike: Change the default bios to use generic platform image riscv: Switch to use generic platform fw_dynamic type opensbi bios images - - 2 - --- 2020-08-03 Bin Meng New
[v6,4/6] hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u riscv: Switch to use generic platform fw_dynamic type opensbi bios images - - 2 - --- 2020-08-03 Bin Meng New
[v6,3/6] roms/Makefile: Build the generic platform for RISC-V OpenSBI firmware riscv: Switch to use generic platform fw_dynamic type opensbi bios images - - 2 - --- 2020-08-03 Bin Meng New
[v6,2/6] roms/opensbi: Upgrade from v0.7 to v0.8 riscv: Switch to use generic platform fw_dynamic type opensbi bios images - - 2 - --- 2020-08-03 Bin Meng New
[v6,1/6] configure: Create symbolic links for pc-bios/*.elf files riscv: Switch to use generic platform fw_dynamic type opensbi bios images - - 1 - --- 2020-08-03 Bin Meng New
hw/riscv: sifive_u: Add a dummy L2 cache controller device hw/riscv: sifive_u: Add a dummy L2 cache controller device - - 1 - --- 2020-07-20 Bin Meng New
hw/riscv: sifive_e: Correct debug block size hw/riscv: sifive_e: Correct debug block size - - 1 - --- 2020-07-16 Bin Meng New
[v2,2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running … [v2,1/2] hw/riscv: Modify MROM size to end at 0x10000 - - - - --- 2020-07-09 Bin Meng New
[v2,1/2] hw/riscv: Modify MROM size to end at 0x10000 [v2,1/2] hw/riscv: Modify MROM size to end at 0x10000 - - 1 - --- 2020-07-09 Bin Meng New
hw/riscv: virt: Sort the SoC memmap table entries hw/riscv: virt: Sort the SoC memmap table entries - - 1 - --- 2020-07-03 Bin Meng New
MAINTAINERS: Add an entry for OpenSBI firmware MAINTAINERS: Add an entry for OpenSBI firmware - - 1 - --- 2020-06-26 Bin Meng New
[v2,5/5] hw/riscv: sifive_u: Add a dummy DDR memory controller device hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-16 Bin Meng New
[v2,4/5] hw/riscv: sifive_u: Sort the SoC memmap table entries hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-16 Bin Meng New
[v2,3/5] hw/riscv: sifive_u: Support different boot source per MSEL pin state hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-16 Bin Meng New
[v2,2/5] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-16 Bin Meng New
[v2,1/5] target/riscv: Rename IBEX CPU init routine hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-16 Bin Meng New
[v2,4/4] riscv: Keep the CPU init routine names consistent [v2,1/4] riscv: Generalize CPU init routine for the base CPU - - 1 - --- 2020-06-11 Bin Meng New
[v2,3/4] riscv: Generalize CPU init routine for the imacu CPU [v2,1/4] riscv: Generalize CPU init routine for the base CPU - - 1 - --- 2020-06-11 Bin Meng New
[v2,2/4] riscv: Generalize CPU init routine for the gcsu CPU [v2,1/4] riscv: Generalize CPU init routine for the base CPU - - 1 - --- 2020-06-11 Bin Meng New
[v2,1/4] riscv: Generalize CPU init routine for the base CPU [v2,1/4] riscv: Generalize CPU init routine for the base CPU - - 1 - --- 2020-06-11 Bin Meng New
[15/15] hw/riscv: sifive_u: Add a dummy DDR memory controller device hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[14/15] hw/riscv: sifive_u: Sort the SoC memmap table entries hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[13/15] hw/riscv: sifive_u: Support different boot source per MSEL pin state hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[12/15] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - - - --- 2020-06-08 Bin Meng New
[11/15] hw/riscv: sifive_u: Add a new property msel for MSEL pin state hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[10/15] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[09/15] hw/riscv: sifive_u: Add reset functionality hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[08/15] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[07/15] hw/riscv: sifive_u: Hook a GPIO controller hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[06/15] hw/riscv: sifive_gpio: Add a new 'ngpio' property hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[05/15] hw/riscv: sifive_gpio: Clean up the codes hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[04/15] hw/riscv: sifive_u: Generate device tree node for OTP hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[03/15] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[02/15] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[01/15] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[2/2] hw/riscv: virt: Remove the riscv_ prefix of the machine* functions [1/2] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions - - 2 - --- 2020-05-21 Bin Meng New
[1/2] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions [1/2] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions - - 2 - --- 2020-05-21 Bin Meng New
[5/5] riscv: Suppress the error report for QEMU testing with riscv_find_firmware() riscv: Switch to use generic platform of opensbi bios images - - 1 - --- 2020-05-01 Bin Meng New
[4/5] riscv/spike: Change the default bios to use generic platform image riscv: Switch to use generic platform of opensbi bios images - - 2 - --- 2020-05-01 Bin Meng New
[3/5] riscv: Use pre-built bios image of generic platform for virt & sifive_u riscv: Switch to use generic platform of opensbi bios images - - 2 - --- 2020-05-01 Bin Meng New
[2/5] gitlab-ci/opensbi: Update GitLab CI to build generic platform riscv: Switch to use generic platform of opensbi bios images - - 1 - --- 2020-05-01 Bin Meng New
[1/5] roms/opensbi: Update to support building bios images for generic platform riscv: Switch to use generic platform of opensbi bios images - - 1 - --- 2020-05-01 Bin Meng New
riscv/spike: Change the default bios to use plain binary image riscv/spike: Change the default bios to use plain binary image - - - - --- 2020-05-01 Bin Meng New
riscv: Change the default behavior if no -bios option is specified riscv: Change the default behavior if no -bios option is specified - - 1 - --- 2020-05-01 Bin Meng New
roms: opensbi: Upgrade from v0.6 to v0.7 roms: opensbi: Upgrade from v0.6 to v0.7 - - 1 - --- 2020-04-20 Bin Meng New
hw/riscv: Generate correct "mmu-type" for 32-bit machines hw/riscv: Generate correct "mmu-type" for 32-bit machines - - 1 - --- 2020-03-07 Bin Meng New
[v2,4/4] gitlab-ci.yml: Add jobs to build OpenSBI firmware binaries riscv: Upgrade OpenSBI to v0.6 and add 32-bit sifive_u bios image 1 - - - --- 2020-02-24 Bin Meng New
[v2,3/4] riscv: sifive_u: Update BIOS_FILENAME for 32-bit riscv: Upgrade OpenSBI to v0.6 and add 32-bit sifive_u bios image - - 1 - --- 2020-02-24 Bin Meng New
[v2,2/4] roms: opensbi: Add 32-bit firmware image for sifive_u machine riscv: Upgrade OpenSBI to v0.6 and add 32-bit sifive_u bios image - - 1 - --- 2020-02-24 Bin Meng New
[v2,1/4] roms: opensbi: Upgrade from v0.5 to v0.6 riscv: Upgrade OpenSBI to v0.6 and add 32-bit sifive_u bios image - - 1 - --- 2020-02-24 Bin Meng New
[v2] riscv: sifive_u: Add a "serial" property for board serial number [v2] riscv: sifive_u: Add a "serial" property for board serial number - - 1 - --- 2020-02-16 Bin Meng New
riscv: virt: Allow PCI address 0 riscv: virt: Allow PCI address 0 - - 1 - --- 2019-11-22 Bin Meng New
[v2,2/2] riscv: sifive_u: Add ethernet0 to the aliases node [v2,1/2] riscv: hw: Drop "clock-frequency" property of cpu nodes - - 2 - --- 2019-09-21 Bin Meng New
[v2,1/2] riscv: hw: Drop "clock-frequency" property of cpu nodes [v2,1/2] riscv: hw: Drop "clock-frequency" property of cpu nodes - - 1 - --- 2019-09-21 Bin Meng New
riscv: Skip checking CSR privilege level in debugger mode riscv: Skip checking CSR privilege level in debugger mode - - 1 - --- 2019-09-20 Bin Meng New
[v8,32/32] riscv: sifive_u: Update model and compatible strings in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,31/32] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,30/32] riscv: sifive_u: Fix broken GEM support riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,29/32] riscv: sifive_u: Instantiate OTP memory with a serial number riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,28/32] riscv: sifive: Implement a model for SiFive FU540 OTP riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,27/32] riscv: roms: Update default bios for sifive_u machine riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,26/32] riscv: sifive_u: Change UART node name in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,25/32] riscv: sifive_u: Update UART base addresses and IRQs riscv: sifive_u: Improve the emulation fidelity of sifive_u machine 1 - 2 - --- 2019-09-06 Bin Meng New
[v8,24/32] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,23/32] riscv: sifive_u: Add PRCI block to the SoC riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,22/32] riscv: sifive_u: Generate hfclk and rtcclk nodes riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,21/32] riscv: sifive: Implement PRCI model for FU540 riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - --- 2019-09-06 Bin Meng New
[v8,20/32] riscv: sifive_u: Update PLIC hart topology configuration string riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,19/32] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,18/32] riscv: sifive_u: Set the minimum number of cpus to 2 riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,17/32] riscv: hart: Add a "hartid-base" property to RISC-V hart array riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,16/32] riscv: hart: Extract hart realize to a separate routine riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,15/32] riscv: Add a sifive_cpu.h to include both E and U cpu type defines riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - --- 2019-09-06 Bin Meng New
[v8,14/32] riscv: sifive_e: Drop sifive_mmio_emulate() riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,13/32] riscv: sifive_e: prci: Update the PRCI register block size riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - --- 2019-09-06 Bin Meng New
[v8,12/32] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming riscv: sifive_u: Improve the emulation fidelity of sifive_u machine 1 - 2 - --- 2019-09-06 Bin Meng New
[v8,11/32] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - --- 2019-09-06 Bin Meng New
[v8,10/32] riscv: sifive_u: Remove the unnecessary include of prci header riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,08/32] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,07/32] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,06/32] riscv: hw: Change create_fdt() to return void riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 3 - --- 2019-09-06 Bin Meng New
[v8,05/32] riscv: hw: Remove not needed PLIC properties in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - --- 2019-09-06 Bin Meng New
[v8,04/32] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,03/32] riscv: hw: Remove superfluous "linux, phandle" property riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,02/32] riscv: sifive_test: Add reset functionality riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,01/32] riscv: hw: Remove duplicated "hw/hw.h" inclusion [v8,01/32] riscv: hw: Remove duplicated "hw/hw.h" inclusion - 1 1 - --- 2019-09-06 Bin Meng New
[v2] riscv: sifive_test: Add reset functionality [v2] riscv: sifive_test: Add reset functionality - - 1 - --- 2019-09-05 Bin Meng New
[2/2] riscv: Resolve full path of the given bios image riscv: Fix "-L" not working for bios image search path - - 1 - --- 2019-08-16 Bin Meng New
[1/2] riscv: Add a helper routine for finding firmware riscv: Fix "-L" not working for bios image search path - - - - --- 2019-08-16 Bin Meng New
[v4] riscv: hmp: Add a command to show virtual memory mappings [v4] riscv: hmp: Add a command to show virtual memory mappings 1 - 1 - --- 2019-08-14 Bin Meng New
[v3] hw: net: cadence_gem: Fix build errors in DB_PRINT() [v3] hw: net: cadence_gem: Fix build errors in DB_PRINT() - - 1 - --- 2019-08-09 Bin Meng New
[v2] riscv: rv32: Root page table address can be larger than 32-bit [v2] riscv: rv32: Root page table address can be larger than 32-bit - - 1 - --- 2019-08-08 Bin Meng New
[FOR,4.1] riscv: roms: Fix make rules for building sifive_u bios [FOR,4.1] riscv: roms: Fix make rules for building sifive_u bios - - 2 - --- 2019-08-03 Bin Meng New
riscv: sifive_e: Correct various SoC IP block sizes riscv: sifive_e: Correct various SoC IP block sizes - - 1 - --- 2019-08-03 Bin Meng New
riscv: sifive_test: Add reset functionality riscv: sifive_test: Add reset functionality - - 1 - --- 2019-06-14 Bin Meng New
riscv: virt: Correct pci "bus-range" encoding riscv: virt: Correct pci "bus-range" encoding - - 1 - --- 2019-05-29 Bin Meng New
[2/2] riscv: sifive_u: Update the plic hartconfig to support multicore Untitled series #108442 - - 1 - --- 2019-05-17 Bin Meng New
[2/2] riscv: sifive_u: Correct UART0's IRQ in the device tree [1/2] riscv: sifive_uart: Generate TX interrupt - - 1 - --- 2019-03-17 Bin Meng New
[1/2] riscv: sifive_uart: Generate TX interrupt [1/2] riscv: sifive_uart: Generate TX interrupt - - 1 - --- 2019-03-17 Bin Meng New
« 1 2 3 »