Show patches with: Submitter = Bin Meng       |    State = Action Required       |    Archived = No       |   301 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
MAINTAINERS: Add an entry for OpenSBI firmware MAINTAINERS: Add an entry for OpenSBI firmware - - 1 - --- 2020-06-26 Bin Meng New
Make ram_addr_t 64 bits unconditionally Make ram_addr_t 64 bits unconditionally - - - - --- 2021-02-19 Bin Meng New
[01/12] hw/riscv: Move sifive_e_prci model to hw/misc hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[01/15] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[02/12] hw/riscv: Move sifive_u_prci model to hw/misc hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[02/15] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[03/12] hw/riscv: Move sifive_u_otp model to hw/misc hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[03/15] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[04/12] hw/riscv: Move sifive_gpio model to hw/gpio hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[04/15] hw/riscv: sifive_u: Generate device tree node for OTP hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[05/12] hw/riscv: Move sifive_clint model to hw/intc hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[05/15] hw/riscv: sifive_gpio: Clean up the codes hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[06/12] hw/riscv: Move sifive_plic model to hw/intc hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[06/15] hw/riscv: sifive_gpio: Add a new 'ngpio' property hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[07/12] hw/riscv: Move riscv_htif model to hw/char hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[07/15] hw/riscv: sifive_u: Hook a GPIO controller hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[08/12] hw/riscv: Move sifive_uart model to hw/char hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[08/15] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[09/12] hw/riscv: Move sifive_test model to hw/misc hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[09/15] hw/riscv: sifive_u: Add reset functionality hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[1/2] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register [1/2] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register - - 1 - --- 2021-03-22 Bin Meng New
[1/2] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions [1/2] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions - - 2 - --- 2020-05-21 Bin Meng New
[1/2] hw/usb: hcd-xhci-pci: Raise MSI/MSI-X interrupts only when told to [1/2] hw/usb: hcd-xhci-pci: Raise MSI/MSI-X interrupts only when told to - 1 1 - --- 2021-05-21 Bin Meng New
[1/2] riscv: Add a helper routine for finding firmware riscv: Fix "-L" not working for bios image search path - - - - --- 2019-08-16 Bin Meng New
[1/2] riscv: sifive_uart: Generate TX interrupt [1/2] riscv: sifive_uart: Generate TX interrupt - - 1 - --- 2019-03-17 Bin Meng New
[1/2] target/riscv: csr: Fix hmode32() for RV64 [1/2] target/riscv: csr: Fix hmode32() for RV64 - - - - --- 2021-03-31 Bin Meng New
[1/4] target/riscv: Make csr_ops[CSR_TABLE_SIZE] external target/riscv: Generate the GDB XML file for CSR registers dynamically - - 2 - --- 2021-01-12 Bin Meng New
[1/5] roms/opensbi: Update to support building bios images for generic platform riscv: Switch to use generic platform of opensbi bios images - - 1 - --- 2020-05-01 Bin Meng New
[1/9] hw/block: m25p80: Fix the number of dummy bytes needed for Windbond flashes hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands - 3 - - --- 2021-01-14 Bin Meng New
[1/9] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - - - --- 2020-10-27 Bin Meng New
[10/12] hw/riscv: Always build riscv_hart.c hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[10/15] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[11/12] hw/riscv: Drop CONFIG_SIFIVE hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[11/15] hw/riscv: sifive_u: Add a new property msel for MSEL pin state hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[12/12] hw/riscv: Sort the Kconfig options in alphabetical order hw/riscv: Clean up the directory - - 1 - --- 2020-09-03 Bin Meng New
[12/15] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - - - --- 2020-06-08 Bin Meng New
[13/15] hw/riscv: sifive_u: Support different boot source per MSEL pin state hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[14/15] hw/riscv: sifive_u: Sort the SoC memmap table entries hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[15/15] hw/riscv: sifive_u: Add a dummy DDR memory controller device hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[2/2] docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine [1/2] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register - - 2 - --- 2021-03-22 Bin Meng New
[2/2] hw/riscv: virt: Remove the riscv_ prefix of the machine* functions [1/2] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions - - 2 - --- 2020-05-21 Bin Meng New
[2/2] hw/usb: hcd-xhci-pci: Fix spec violation of IP flag for MSI/MSI-X [1/2] hw/usb: hcd-xhci-pci: Raise MSI/MSI-X interrupts only when told to - 2 1 - --- 2021-05-21 Bin Meng New
[2/2] riscv: Resolve full path of the given bios image riscv: Fix "-L" not working for bios image search path - - 1 - --- 2019-08-16 Bin Meng New
[2/2] riscv: sifive_u: Correct UART0's IRQ in the device tree [1/2] riscv: sifive_uart: Generate TX interrupt - - 1 - --- 2019-03-17 Bin Meng New
[2/2] riscv: sifive_u: Update the plic hartconfig to support multicore Untitled series #108442 - - 1 - --- 2019-05-17 Bin Meng New
[2/2] target/riscv: csr: Remove redundant check in fp csr read/write routines [1/2] target/riscv: csr: Fix hmode32() for RV64 - - 1 - --- 2021-03-31 Bin Meng New
[2/4] target/riscv: Add CSR name in the CSR function table target/riscv: Generate the GDB XML file for CSR registers dynamically - - 1 - --- 2021-01-12 Bin Meng New
[2/5] gitlab-ci/opensbi: Update GitLab CI to build generic platform riscv: Switch to use generic platform of opensbi bios images - - 1 - --- 2020-05-01 Bin Meng New
[2/9] hw/block: m25p80: Fix the number of dummy bytes needed for Numonyx/Micron flashes hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands - 1 - - --- 2021-01-14 Bin Meng New
[2/9] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - - - --- 2020-10-27 Bin Meng New
[3/5] riscv: Use pre-built bios image of generic platform for virt & sifive_u riscv: Switch to use generic platform of opensbi bios images - - 2 - --- 2020-05-01 Bin Meng New
[3/9] hw/block: m25p80: Fix the number of dummy bytes needed for Macronix flashes hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands - 1 - - --- 2021-01-14 Bin Meng New
[4/5] riscv/spike: Change the default bios to use generic platform image riscv: Switch to use generic platform of opensbi bios images - - 2 - --- 2020-05-01 Bin Meng New
[4/9] hw/block: m25p80: Fix the number of dummy bytes needed for Spansion flashes hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands - - - - --- 2021-01-14 Bin Meng New
[5/5] riscv: Suppress the error report for QEMU testing with riscv_find_firmware() riscv: Switch to use generic platform of opensbi bios images - - 1 - --- 2020-05-01 Bin Meng New
[5/9] hw/block: m25p80: Support fast read for SST flashes hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands - - - - --- 2021-01-14 Bin Meng New
[6/9] hw/ssi: xilinx_spips: Fix generic fifo dummy cycle handling hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands - 1 - - --- 2021-01-14 Bin Meng New
[7/9] Revert "aspeed/smc: Fix number of dummy cycles for FAST_READ_4 command" hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands - - - - --- 2021-01-14 Bin Meng New
[8/9] Revert "aspeed/smc: snoop SPI transfers to fake dummy cycles" hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands - - - - --- 2021-01-14 Bin Meng New
[9/9] hw/ssi: npcm7xx_fiu: Correct the dummy cycle emulation logic hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands - - - - --- 2021-01-14 Bin Meng New
[FOR,4.1] riscv: roms: Fix make rules for building sifive_u bios [FOR,4.1] riscv: roms: Fix make rules for building sifive_u bios - - 2 - --- 2019-08-03 Bin Meng New
[RESEND,6/9] hw/riscv: microchip_pfsoc: Connect the SYSREG module hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-27 Bin Meng New
[RESEND,v2] hw/intc: Move sifive_plic.h to the include directory [RESEND,v2] hw/intc: Move sifive_plic.h to the include directory - 1 1 - --- 2020-10-13 Bin Meng New
[RESEND,v3,1/5] hw/sd: sdhci: Don't transfer any data when command time out hw/sd: sdhci: Fixes to CVE-2020-17380, CVE-2020-25085, CVE-2021-3409 1 4 - 2 --- 2021-03-03 Bin Meng New
[RESEND,v3,2/5] hw/sd: sdhci: Don't write to SDHC_SYSAD register when transfer is in progress hw/sd: sdhci: Fixes to CVE-2020-17380, CVE-2020-25085, CVE-2021-3409 - 4 - 1 --- 2021-03-03 Bin Meng New
[RESEND,v3,3/5] hw/sd: sdhci: Correctly set the controller status for ADMA hw/sd: sdhci: Fixes to CVE-2020-17380, CVE-2020-25085, CVE-2021-3409 - 4 1 1 --- 2021-03-03 Bin Meng New
[RESEND,v3,4/5] hw/sd: sdhci: Limit block size only when SDHC_BLKSIZE register is writable hw/sd: sdhci: Fixes to CVE-2020-17380, CVE-2020-25085, CVE-2021-3409 - - 1 1 --- 2021-03-03 Bin Meng New
[RESEND,v3,5/5] hw/sd: sdhci: Reset the data pointer of s->fifo_buffer[] when a different block siz… hw/sd: sdhci: Fixes to CVE-2020-17380, CVE-2020-25085, CVE-2021-3409 - 4 - 1 --- 2021-03-03 Bin Meng New
[RESEND] hw/ppc: e500: Add missing #address-cells and #size-cells in the eTSEC node [RESEND] hw/ppc: e500: Add missing #address-cells and #size-cells in the eTSEC node - 1 - - --- 2021-03-11 Bin Meng New
[for-6.0,1/3] roms/Makefile: Update ppce500 u-boot build directory name [for-6.0,1/3] roms/Makefile: Update ppce500 u-boot build directory name - - - - --- 2021-04-06 Bin Meng New
[for-6.0,2/3] roms/u-boot: Bump ppce500 u-boot to v2021.04 to fix broken pci support [for-6.0,1/3] roms/Makefile: Update ppce500 u-boot build directory name - - - - --- 2021-04-06 Bin Meng New
[for-6.0,3/3] docs/system: ppc: Add documentation for ppce500 machine [for-6.0,1/3] roms/Makefile: Update ppce500 u-boot build directory name - - - - --- 2021-04-06 Bin Meng New
[v2,01/10] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-28 Bin Meng New
[v2,01/25] hw/block: m25p80: Add ISSI SPI flash support hw/riscv: sifive_u: Add missing SPI support - - - - --- 2021-01-23 Bin Meng New
[v2,02/10] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-28 Bin Meng New
[v2,02/25] hw/block: m25p80: Add various ISSI flash information hw/riscv: sifive_u: Add missing SPI support 1 - - - --- 2021-01-23 Bin Meng New
[v2,03/10] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-28 Bin Meng New
[v2,03/25] hw/sd: ssi-sd: Fix incorrect card response sequence hw/riscv: sifive_u: Add missing SPI support - 1 2 1 --- 2021-01-23 Bin Meng New
[v2,04/10] hw/misc: Add Microchip PolarFire SoC IOSCB module support hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-28 Bin Meng New
[v2,04/25] hw/sd: sd: Support CMD59 for SPI mode hw/riscv: sifive_u: Add missing SPI support - - 2 1 --- 2021-01-23 Bin Meng New
[v2,05/10] hw/riscv: microchip_pfsoc: Connect the IOSCB module hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-28 Bin Meng New
[v2,05/25] hw/sd: sd: Drop sd_crc16() hw/riscv: sifive_u: Add missing SPI support - - 2 1 --- 2021-01-23 Bin Meng New
[v2,06/10] hw/misc: Add Microchip PolarFire SoC SYSREG module support hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-28 Bin Meng New
[v2,06/25] util: Add CRC16 (CCITT) calculation routines hw/riscv: sifive_u: Add missing SPI support 1 - 1 - --- 2021-01-23 Bin Meng New
[v2,07/10] hw/riscv: microchip_pfsoc: Connect the SYSREG module hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-28 Bin Meng New
[v2,07/25] hw/sd: ssi-sd: Suffix a data block with CRC16 hw/riscv: sifive_u: Add missing SPI support 1 1 1 - --- 2021-01-23 Bin Meng New
[v2,08/10] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-28 Bin Meng New
[v2,08/25] hw/sd: ssi-sd: Add a state representing Nac hw/riscv: sifive_u: Add missing SPI support 1 - - - --- 2021-01-23 Bin Meng New
[v2,09/10] hw/riscv: microchip_pfsoc: Correct DDR memory map hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box - - 1 - --- 2020-10-28 Bin Meng New
[v2,09/25] hw/sd: ssi-sd: Fix the wrong command index for STOP_TRANSMISSION hw/riscv: sifive_u: Add missing SPI support - 1 1 - --- 2021-01-23 Bin Meng New
[v2,1/2] hw/ppc: e500: Use a macro for the platform clock frequency [v2,1/2] hw/ppc: e500: Use a macro for the platform clock frequency - - 1 - --- 2021-02-03 Bin Meng New
[v2,1/2] hw/riscv: Modify MROM size to end at 0x10000 [v2,1/2] hw/riscv: Modify MROM size to end at 0x10000 - - 1 - --- 2020-07-09 Bin Meng New
[v2,1/2] riscv: hw: Drop "clock-frequency" property of cpu nodes [v2,1/2] riscv: hw: Drop "clock-frequency" property of cpu nodes - - 1 - --- 2019-09-21 Bin Meng New
[v2,1/2] target/riscv: Generate the GDB XML file for CSR registers dynamically target/riscv: Generate the GDB XML file for CSR registers dynamically - - 1 - --- 2021-01-16 Bin Meng New
[v2,1/3] net: checksum: Skip fragmented IP packets [v2,1/3] net: checksum: Skip fragmented IP packets - - - - --- 2020-12-11 Bin Meng New
[v2,1/4] riscv: Generalize CPU init routine for the base CPU [v2,1/4] riscv: Generalize CPU init routine for the base CPU - - 1 - --- 2020-06-11 Bin Meng New
[v2,1/4] roms: opensbi: Upgrade from v0.5 to v0.6 riscv: Upgrade OpenSBI to v0.6 and add 32-bit sifive_u bios image - - 1 - --- 2020-02-24 Bin Meng New
[v2,1/5] target/riscv: Rename IBEX CPU init routine hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-16 Bin Meng New
[v2,1/8] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper [v2,1/8] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 1 - --- 2021-04-30 Bin Meng New
[v2,1/8] hw/sd: sd: Fix address check in sd_erase() hw/sd: sd: Erase operation and other fixes - 1 1 - --- 2021-02-16 Bin Meng New
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