Show patches with: Submitter = Greg Bellows       |    State = Action Required       |    Archived = No       |   403 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v4,01/33] target-arm: add cpu feature EL3 to CPUs with Security Extensions - - - - --- 2014-06-30 Greg Bellows New
[v4,02/33] target-arm: move Aarch32 SCR into security reglist - - 1 - --- 2014-06-30 Greg Bellows New
[v4,03/33] target-arm: increase arrays of registers R13 & R14 - - 1 - --- 2014-06-30 Greg Bellows New
[v4,04/33] target-arm: add arm_is_secure() function - - - - --- 2014-06-30 Greg Bellows New
[v4,05/33] target-arm: reject switching to monitor mode - - 1 - --- 2014-06-30 Greg Bellows New
[v4,06/33] target-arm: make arm_current_pl() return PL3 - - - - --- 2014-06-30 Greg Bellows New
[v4,07/33] target-arm: add non-secure Translation Block flag - - 1 - --- 2014-06-30 Greg Bellows New
[v4,08/33] target-arm: A32: Emulate the SMC instruction - - - - --- 2014-06-30 Greg Bellows New
[v4,09/33] target-arm: extend Aarch32 async excp masking - - - - --- 2014-06-30 Greg Bellows New
[v4,10/33] target-arm: extend Aarch64 SCR.{FIQ|IRQ} handling - - - - --- 2014-06-30 Greg Bellows New
[v4,11/33] target-arm: add async excp target_el&mode function - - - - --- 2014-06-30 Greg Bellows New
[v4,12/33] target-arm: use dedicated target_el function - - - - --- 2014-06-30 Greg Bellows New
[v4,13/33] target-arm: implement IRQ/FIQ routing to Monitor mode - - - - --- 2014-06-30 Greg Bellows New
[v4,14/33] target-arm: Respect SCR.FW, SCR.AW and SCTLR.NMFI - - - - --- 2014-06-30 Greg Bellows New
[v4,15/33] target-arm: add NSACR register - - - - --- 2014-06-30 Greg Bellows New
[v4,16/33] target-arm: add SDER definition - - - - --- 2014-06-30 Greg Bellows New
[v4,17/33] target-arm: add MVBAR support - - - - --- 2014-06-30 Greg Bellows New
[v4,18/33] target-arm: add macros to access banked registers - - - - --- 2014-06-30 Greg Bellows New
[v4,19/33] target-arm: insert Aarch32 cpregs twice into hashtable - - - - --- 2014-06-30 Greg Bellows New
[v4,20/33] target-arm: arrayfying fieldoffset for banking - - - - --- 2014-06-30 Greg Bellows New
[v4,21/33] target-arm: add SCTLR_EL3 and make SCTLR banked - - - - --- 2014-06-30 Greg Bellows New
[v4,22/33] target-arm: make CSSELR banked - - - - --- 2014-06-30 Greg Bellows New
[v4,23/33] target-arm: add TTBR0_EL3 and make TTBR0/1 banked - - - - --- 2014-06-30 Greg Bellows New
[v4,24/33] target-arm: add TCR_EL3 and make TTBCR banked - - - - --- 2014-06-30 Greg Bellows New
[v4,25/33] target-arm: make c2_mask and c2_base_mask banked - - - - --- 2014-06-30 Greg Bellows New
[v4,26/33] target-arm: make DACR banked - - - - --- 2014-06-30 Greg Bellows New
[v4,27/33] target-arm: make IFSR banked - - - - --- 2014-06-30 Greg Bellows New
[v4,28/33] target-arm: make DFSR banked - - - - --- 2014-06-30 Greg Bellows New
[v4,29/33] target-arm: make IFAR/DFAR banked - - - - --- 2014-06-30 Greg Bellows New
[v4,30/33] target-arm: make PAR banked - - - - --- 2014-06-30 Greg Bellows New
[v4,31/33] target-arm: make VBAR banked - - - - --- 2014-06-30 Greg Bellows New
[v4,32/33] target-arm: make c13 cp regs banked (FCSEIDR, ...) - - - - --- 2014-06-30 Greg Bellows New
[v4,33/33] target-arm: Limit migration of duplicate CP regs - - - - --- 2014-06-30 Greg Bellows New
[v5,01/33] target-arm: increase arrays of registers R13 & R14 - - 1 - --- 2014-09-30 Greg Bellows New
[v5,02/33] target-arm: add arm_is_secure() function - - - - --- 2014-09-30 Greg Bellows New
[v5,03/33] target-arm: reject switching to monitor mode - - 2 - --- 2014-09-30 Greg Bellows New
[v5,04/33] target-arm: rename arm_current_pl to arm_current_el - - - - --- 2014-09-30 Greg Bellows New
[v5,05/33] target-arm: make arm_current_pl() return PL3 - - - - --- 2014-09-30 Greg Bellows New
[v5,06/33] target-arm: A32: Emulate the SMC instruction - - - - --- 2014-09-30 Greg Bellows New
[v5,07/33] target-arm: extend async excp masking - - - - --- 2014-09-30 Greg Bellows New
[v5,08/33] target-arm: add async excp target_el function - - - - --- 2014-09-30 Greg Bellows New
[v5,09/33] target-arm: add macros to access banked registers - - - - --- 2014-09-30 Greg Bellows New
[v5,10/33] target-arm: add non-secure Translation Block flag - - - - --- 2014-09-30 Greg Bellows New
[v5,11/33] target-arm: arrayfying fieldoffset for banking - - - - --- 2014-09-30 Greg Bellows New
[v5,12/33] target-arm: insert Aarch32 cpregs twice into hashtable - - - - --- 2014-09-30 Greg Bellows New
[v5,13/33] target-arm: move Aarch32 SCR into security reglist - - - - --- 2014-09-30 Greg Bellows New
[v5,14/33] target-arm: implement IRQ/FIQ routing to Monitor mode - - - - --- 2014-09-30 Greg Bellows New
[v5,15/33] target-arm: Respect SCR.FW, SCR.AW and SCTLR.NMFI - - - - --- 2014-09-30 Greg Bellows New
[v5,16/33] target-arm: add NSACR register - - - - --- 2014-09-30 Greg Bellows New
[v5,17/33] target-arm: add SDER definition - - - - --- 2014-09-30 Greg Bellows New
[v5,18/33] target-arm: add MVBAR support - - - - --- 2014-09-30 Greg Bellows New
[v5,19/33] target-arm: add SCTLR_EL3 and make SCTLR banked - - - - --- 2014-09-30 Greg Bellows New
[v5,20/33] target-arm: make CSSELR banked - - - - --- 2014-09-30 Greg Bellows New
[v5,21/33] target-arm: add TTBR0_EL3 and make TTBR0/1 banked - - - - --- 2014-09-30 Greg Bellows New
[v5,22/33] target-arm: add TCR_EL3 and make TTBCR banked - - - - --- 2014-09-30 Greg Bellows New
[v5,23/33] target-arm: make c2_mask and c2_base_mask banked - - - - --- 2014-09-30 Greg Bellows New
[v5,24/33] target-arm: make DACR banked - - - - --- 2014-09-30 Greg Bellows New
[v5,25/33] target-arm: make IFSR banked - - - - --- 2014-09-30 Greg Bellows New
[v5,26/33] target-arm: make DFSR banked - - - - --- 2014-09-30 Greg Bellows New
[v5,27/33] target-arm: make IFAR/DFAR banked - - - - --- 2014-09-30 Greg Bellows New
[v5,28/33] target-arm: make PAR banked - - - - --- 2014-09-30 Greg Bellows New
[v5,29/33] target-arm: make VBAR banked - - - - --- 2014-09-30 Greg Bellows New
[v5,30/33] target-arm: make MAIR0/1 banked - - - - --- 2014-09-30 Greg Bellows New
[v5,31/33] target-arm: make c13 cp regs banked (FCSEIDR, ...) - - - - --- 2014-09-30 Greg Bellows New
[v5,32/33] target-arm: add GDB scr register - - - - --- 2014-09-30 Greg Bellows New
[v5,33/33] target-arm: add cpu feature EL3 to CPUs with Security Extensions - - - - --- 2014-09-30 Greg Bellows New
target-arm: add second UART to virt - - - - --- 2014-10-08 Greg Bellows New
[v6,01/32] target-arm: increase arrays of registers R13 & R14 - - 1 - --- 2014-10-10 Greg Bellows New
[v6,02/32] target-arm: add arm_is_secure() function - - - - --- 2014-10-10 Greg Bellows New
[v6,03/32] target-arm: reject switching to monitor mode - - 2 - --- 2014-10-10 Greg Bellows New
[v6,04/32] target-arm: rename arm_current_pl to arm_current_el - - 1 - --- 2014-10-10 Greg Bellows New
[v6,05/32] target-arm: make arm_current_el() return EL3 - - 1 - --- 2014-10-10 Greg Bellows New
[v6,06/32] target-arm: A32: Emulate the SMC instruction - - - - --- 2014-10-10 Greg Bellows New
[v6,07/32] target-arm: extend async excp masking - - - - --- 2014-10-10 Greg Bellows New
[v6,08/32] target-arm: add async excp target_el function - - - - --- 2014-10-10 Greg Bellows New
[v6,09/32] target-arm: add banked register accessors - - - - --- 2014-10-10 Greg Bellows New
[v6,10/32] target-arm: add non-secure Translation Block flag - - - - --- 2014-10-10 Greg Bellows New
[v6,11/32] target-arm: add CPREG secure state support - - - - --- 2014-10-10 Greg Bellows New
[v6,12/32] target-arm: add secure state bit to CPREG hash - - - - --- 2014-10-10 Greg Bellows New
[v6,13/32] target-arm: insert AArch32 cpregs twice into hashtable - - - - --- 2014-10-10 Greg Bellows New
[v6,14/32] target-arm: move AArch32 SCR into security reglist - - - - --- 2014-10-10 Greg Bellows New
[v6,15/32] target-arm: implement IRQ/FIQ routing to Monitor mode - - - - --- 2014-10-10 Greg Bellows New
[v6,16/32] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI - - - - --- 2014-10-10 Greg Bellows New
[v6,17/32] target-arm: add NSACR register - - - - --- 2014-10-10 Greg Bellows New
[v6,18/32] target-arm: add SDER definition - - - - --- 2014-10-10 Greg Bellows New
[v6,19/32] target-arm: add MVBAR support - - - - --- 2014-10-10 Greg Bellows New
[v6,20/32] target-arm: add SCTLR_EL3 and make SCTLR banked - - - - --- 2014-10-10 Greg Bellows New
[v6,21/32] target-arm: make CSSELR banked - - - - --- 2014-10-10 Greg Bellows New
[v6,22/32] target-arm: add TTBR0_EL3 and make TTBR0/1 banked - - - - --- 2014-10-10 Greg Bellows New
[v6,23/32] target-arm: add TCR_EL3 and make TTBCR banked - - - - --- 2014-10-10 Greg Bellows New
[v6,24/32] target-arm: make c2_mask and c2_base_mask banked - - - - --- 2014-10-10 Greg Bellows New
[v6,25/32] target-arm: make DACR banked - - - - --- 2014-10-10 Greg Bellows New
[v6,26/32] target-arm: make IFSR banked - - - - --- 2014-10-10 Greg Bellows New
[v6,27/32] target-arm: make DFSR banked - - - - --- 2014-10-10 Greg Bellows New
[v6,28/32] target-arm: make IFAR/DFAR banked - - - - --- 2014-10-10 Greg Bellows New
[v6,29/32] target-arm: make PAR banked - - - - --- 2014-10-10 Greg Bellows New
[v6,30/32] target-arm: make c13 cp regs banked (FCSEIDR, ...) - - - - --- 2014-10-10 Greg Bellows New
[v6,31/32] target-arm: make MAIR0/1 banked - - - - --- 2014-10-10 Greg Bellows New
[v6,32/32] target-arm: add cpu feature EL3 to CPUs with Security Extensions - - - - --- 2014-10-10 Greg Bellows New
[v7,01/32] target-arm: increase arrays of registers R13 & R14 - - 1 - --- 2014-10-21 Greg Bellows New
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