Show patches with: Series = [1/2] riscv: sifive_uart: Generate TX interrupt       |    State = Action Required       |    Archived = No       |   2 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[2/2] riscv: sifive_u: Correct UART0's IRQ in the device tree [1/2] riscv: sifive_uart: Generate TX interrupt - - 1 - --- 2019-03-17 Bin Meng New
[1/2] riscv: sifive_uart: Generate TX interrupt [1/2] riscv: sifive_uart: Generate TX interrupt - - 1 - --- 2019-03-17 Bin Meng New