Show patches with: Series = [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v       |    State = Action Required       |    Archived = No       |   33 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[PULL,33/33] hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 3 - --- 2021-10-22 Alistair Francis New
[PULL,32/33] hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 3 - --- 2021-10-22 Alistair Francis New
[PULL,31/33] hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 3 - --- 2021-10-22 Alistair Francis New
[PULL,30/33] hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 3 - --- 2021-10-22 Alistair Francis New
[PULL,29/33] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 3 - --- 2021-10-22 Alistair Francis New
[PULL,28/33] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,27/33] hw/intc: sifive_plic: Cleanup the irq_request function [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 1 - --- 2021-10-22 Alistair Francis New
[PULL,26/33] hw/intc: sifive_plic: Cleanup the realize function [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 1 - --- 2021-10-22 Alistair Francis New
[PULL,25/33] hw/intc: sifive_plic: Move the properties [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 1 - --- 2021-10-22 Alistair Francis New
[PULL,24/33] hw/intc: Remove the Ibex PLIC [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 1 - --- 2021-10-22 Alistair Francis New
[PULL,23/33] hw/riscv: opentitan: Update to the latest build [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 1 - --- 2021-10-22 Alistair Francis New
[PULL,22/33] target/riscv: Compute mstatus.sd on demand [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 1 - --- 2021-10-22 Alistair Francis New
[PULL,21/33] target/riscv: Use riscv_csrrw_debug for cpu_dump [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 1 - --- 2021-10-22 Alistair Francis New
[PULL,20/33] target/riscv: Use gen_shift*_per_ol for RVB, RVI [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,19/33] target/riscv: Use gen_unary_per_ol for RVB [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,18/33] target/riscv: Adjust trans_rev8_32 for riscv64 [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v 1 - 1 - --- 2021-10-22 Alistair Francis New
[PULL,17/33] target/riscv: Use gen_arith_per_ol for RVM [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,16/33] target/riscv: Replace DisasContext.w with DisasContext.ol [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,15/33] target/riscv: Replace is_32bit with get_xl/get_xlen [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,14/33] target/riscv: Properly check SEW in amo_op [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,13/33] target/riscv: Use REQUIRE_64BIT in amo_check64 [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,12/33] target/riscv: Add MXL/SXL/UXL to TB_FLAGS [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,11/33] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,10/33] target/riscv: Split misa.mxl and misa.ext [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,09/33] target/riscv: Create RISCVMXL enumeration [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,08/33] target/riscv: Move cpu_get_tb_cpu_state out of line [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,07/33] target/riscv: Organise the CPU properties [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,06/33] target/riscv: Remove some unused macros [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 3 - --- 2021-10-22 Alistair Francis New
[PULL,05/33] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 2 - --- 2021-10-22 Alistair Francis New
[PULL,04/33] hw/riscv: virt: Use machine->ram as the system memory [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 1 - --- 2021-10-22 Alistair Francis New
[PULL,03/33] target/riscv: Fix orc.b implementation [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - 1 1 1 --- 2021-10-22 Alistair Francis New
[PULL,02/33] target/riscv: line up all of the registers in the info register dump [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 1 - --- 2021-10-22 Alistair Francis New
[PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v [PULL,01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v - - 1 - --- 2021-10-22 Alistair Francis New