Show patches with: Series = target/riscv: support packed extension v0.9.4       |    State = Action Required       |    Archived = No       |   37 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v3,37/37] target/riscv: configure and turn on packed extension from command line target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,36/37] target/riscv: RV64 Only 32-bit Packing Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,34/37] target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,32/37] target/riscv: RV64 Only 32-bit Multiply Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,27/37] target/riscv: Non-SIMD Miscellaneous Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,26/37] target/riscv: 32-bit Computation Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,25/37] target/riscv: Non-SIMD Q31 saturation ALU Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,23/37] target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,22/37] target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,21/37] target/riscv: 64-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,19/37] target/riscv: Partial-SIMD Miscellaneous Instructions target/riscv: support packed extension v0.9.4 1 - - - --- 2021-06-24 LIU Zhiwei New
[v3,18/37] target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,16/37] target/riscv: Signed MSW 32x16 Multiply and Add Instructions target/riscv: support packed extension v0.9.4 1 - - - --- 2021-06-24 LIU Zhiwei New
[v3,15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,14/37] target/riscv: 16-bit Packing Instructions target/riscv: support packed extension v0.9.4 1 - - - --- 2021-06-24 LIU Zhiwei New
[v3,13/37] target/riscv: 8-bit Unpacking Instructions target/riscv: support packed extension v0.9.4 1 - - - --- 2021-06-24 LIU Zhiwei New
[v3,12/37] target/riscv: SIMD 8-bit Miscellaneous Instructions target/riscv: support packed extension v0.9.4 1 - - - --- 2021-06-24 LIU Zhiwei New
[v3,11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions target/riscv: support packed extension v0.9.4 1 - - - --- 2021-06-24 LIU Zhiwei New
[v3,10/37] target/riscv: SIMD 8-bit Multiply Instructions target/riscv: support packed extension v0.9.4 1 - - - --- 2021-06-24 LIU Zhiwei New
[v3,09/37] target/riscv: SIMD 16-bit Multiply Instructions target/riscv: support packed extension v0.9.4 - - - - --- 2021-06-24 LIU Zhiwei New
[v3,08/37] target/riscv: SIMD 8-bit Compare Instructions target/riscv: support packed extension v0.9.4 1 - - - --- 2021-06-24 LIU Zhiwei New
[v3,07/37] target/riscv: SIMD 16-bit Compare Instructions target/riscv: support packed extension v0.9.4 1 - - - --- 2021-06-24 LIU Zhiwei New
[v3,06/37] target/riscv: SIMD 8-bit Shift Instructions target/riscv: support packed extension v0.9.4 1 - 1 - --- 2021-06-24 LIU Zhiwei New
[v3,05/37] target/riscv: SIMD 16-bit Shift Instructions target/riscv: support packed extension v0.9.4 - - 1 - --- 2021-06-24 LIU Zhiwei New
[v3,04/37] target/riscv: 8-bit Addition & Subtraction Instruction target/riscv: support packed extension v0.9.4 1 - 1 - --- 2021-06-24 LIU Zhiwei New
[v3,03/37] target/riscv: 16-bit Addition & Subtraction Instructions target/riscv: support packed extension v0.9.4 - - 1 - --- 2021-06-24 LIU Zhiwei New
[v3,02/37] target/riscv: Make the vector helper functions public target/riscv: support packed extension v0.9.4 - - 1 - --- 2021-06-24 LIU Zhiwei New
[v3,01/37] target/riscv: implementation-defined constant parameters target/riscv: support packed extension v0.9.4 - - 1 - --- 2021-06-24 LIU Zhiwei New