Message ID | 20220124075523.108875-1-yang.zhong@intel.com |
---|---|
Headers | show |
Series | AMX support in Qemu | expand |
On 1/24/22 08:55, Yang Zhong wrote: > Intel introduces Advanced Matrix Extensions (AMX) [1] feature that > consists of configurable two-dimensional "TILE" registers and new > accelerator instructions that operate on them. TMUL (Tile matrix > MULtiply) is the first accelerator instruction set to use the new > registers. > > Since AMX KVM patches have been merged into Linux release, this series > is based on latest Linux release. > > According to the KVM design, the userspace VMM (e.g. Qemu) is expected > to request guest permission for the dynamically-enabled XSAVE features > only once when the first vCPU is created, and KVM checks guest permission > in KVM_SET_CPUID2. > > Intel AMX is XSAVE supported and XSAVE enabled. Those extended features > has large state while current kvm_xsave only allows 4KB. The AMX KVM has > extended struct kvm_xsave to meet this requirenment and added one extra > KVM_GET_XSAVE2 ioctl to handle extended features. From our test, the AMX > live migration work well. > > Notice: This version still includes some definitions in the linux-headers, > once Qemu sync those linux-headers, I will remove those definitions. So > please ignore those changes. Yes, no problem with that. I think the KVM API is insufficient and needs a small but important extra feature, equivalent to ARCH_GET_XCOMP_SUPP. We can implement that easily in 5.17 though. Paolo > [1] Intel Architecture Instruction Set Extension Programming Reference > https://software.intel.com/content/dam/develop/external/us/en/documents/\ > architecture-instruction-set-extensions-programming-reference.pdf