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[147.11.176.192]) by smtp.gmail.com with ESMTPSA id q12sm6645790pfk.65.2021.10.29.08.25.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Oct 2021 08:25:43 -0700 (PDT) From: Bin Meng X-Google-Original-From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 0/5] target/riscv: Initial support for native debug feature via M-mode CSRs Date: Fri, 29 Oct 2021 23:25:30 +0800 Message-Id: <20211029152535.2055096-1-bin.meng@windriver.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This adds initial support for the native debug via the Trigger Module, as defined in the RISC-V Debug Specification [1]. Only "Address / Data Match" trigger (type 2) is implemented as of now, which is mainly used for hardware breakpoint and watchpoint. The number of type 2 triggers implemented is 2, which is the number that we can find in the SiFive U54/U74 cores. [1] https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable.pdf Bin Meng (5): target/riscv: Add initial support for native debug target/riscv: debug: Implement debug related TCGCPUOps target/riscv: Add a config option for native debug target/riscv: csr: Hook debug CSR read/write hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() include/hw/core/tcg-cpu-ops.h | 1 + target/riscv/cpu.h | 7 + target/riscv/debug.h | 114 +++++++++ target/riscv/cpu.c | 14 ++ target/riscv/csr.c | 57 +++++ target/riscv/debug.c | 439 ++++++++++++++++++++++++++++++++++ target/riscv/meson.build | 1 + 7 files changed, 633 insertions(+) create mode 100644 target/riscv/debug.h create mode 100644 target/riscv/debug.c