| Message ID | 20211023084638.1697057-1-anup.patel@wdc.com |
|---|---|
| Headers | show |
| Series | QEMU RISC-V AIA support | expand |
Hi Alistair, On Sat, Oct 23, 2021 at 2:17 PM Anup Patel <anup.patel@wdc.com> wrote: > > The advanced interrupt architecture (AIA) extends the per-HART local > interrupt support. Along with this, it also adds IMSIC (MSI contrllor) > and Advanced PLIC (wired interrupt controller). > > The latest AIA draft specification can be found here: > https://github.com/riscv/riscv-aia/releases/download/0.2-draft.27/riscv-interrupts-027.pdf > > This series adds RISC-V AIA support in QEMU which includes emulating all > AIA local CSRs, APLIC, and IMSIC. Only AIA local interrupt filtering is > not implemented because we don't have any local interrupt greater than 12. > > To enable AIA in QEMU, use one of the following: > 1) Only AIA local interrupt CSRs: Pass "x-aia=true" as CPU paramenter > in the QEMU command-line > 2) Only APLIC for virt machine: Pass "aia=aplic" as machine parameter > in the QEMU command-line > 3) Both APLIC and IMSIC for virt machine: Pass "aia=aplic-imsic" as > machine parameter in the QEMU command-line > 4) Both APLIC and IMSIC with 2 guest files for virt machine: Pass > "aia=aplic-imsic,aia-guests=2" as machine parameter in the QEMU > command-line > > To test series, we require OpenSBI and Linux with AIA support which can > be found in riscv_aia_v1 branch at: > https://github.com/avpatel/opensbi.git > https://github.com/avpatel/linux.git > > This series can be found riscv_aia_v3 branch at: > https://github.com/avpatel/qemu.git > > Changes since v2: > - Update PATCH4 to check and inject interrupt after V=1 when > transitioning from V=0 to V=1 > > Changes since v1: > - Revamped whole series and created more granular patches > - Added HGEIE and HGEIP CSR emulation for H-extension > - Added APLIC emulation > - Added IMSIC emulation > > Anup Patel (22): > target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 > HS-mode > target/riscv: Implement SGEIP bit in hip and hie CSRs > target/riscv: Implement hgeie and hgeip CSRs > target/riscv: Improve delivery of guest external interrupts > target/riscv: Allow setting CPU feature from machine/device emulation > target/riscv: Add AIA cpu feature > target/riscv: Add defines for AIA CSRs > target/riscv: Allow AIA device emulation to set ireg rmw callback > target/riscv: Implement AIA local interrupt priorities > target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 > target/riscv: Implement AIA hvictl and hviprioX CSRs > target/riscv: Implement AIA interrupt filtering CSRs > target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs > target/riscv: Implement AIA xiselect and xireg CSRs > target/riscv: Implement AIA IMSIC interface CSRs > hw/riscv: virt: Use AIA INTC compatible string when available > target/riscv: Allow users to force enable AIA CSRs in HART > hw/intc: Add RISC-V AIA APLIC device emulation > hw/riscv: virt: Add optional AIA APLIC support to virt machine > hw/intc: Add RISC-V AIA IMSIC device emulation > hw/riscv: virt: Add optional AIA IMSIC support to virt machine > docs/system: riscv: Document AIA options for virt machine The PATCH19 and PATCH21 uses "aplic,xxx" and "imsic,xxx" DT properties which is not allowed as-per Linux DT schema checker because "aplic" and "imsic" prefixes are not vendor names. Instead of this we should use "riscv" prefix which is registered vendor in Linux DT bindings. I will send v4 to fix the above. Regards, Anup > > docs/system/riscv/virt.rst | 16 + > hw/intc/Kconfig | 6 + > hw/intc/meson.build | 2 + > hw/intc/riscv_aplic.c | 970 +++++++++++++++++++++++++ > hw/intc/riscv_imsic.c | 443 ++++++++++++ > hw/riscv/Kconfig | 2 + > hw/riscv/virt.c | 694 +++++++++++++++--- > include/hw/intc/riscv_aplic.h | 73 ++ > include/hw/intc/riscv_imsic.h | 68 ++ > include/hw/riscv/virt.h | 40 +- > target/riscv/cpu.c | 97 ++- > target/riscv/cpu.h | 67 +- > target/riscv/cpu_bits.h | 132 ++++ > target/riscv/cpu_helper.c | 300 +++++++- > target/riscv/csr.c | 1273 ++++++++++++++++++++++++++++++--- > target/riscv/machine.c | 24 +- > 16 files changed, 3901 insertions(+), 306 deletions(-) > create mode 100644 hw/intc/riscv_aplic.c > create mode 100644 hw/intc/riscv_imsic.c > create mode 100644 include/hw/intc/riscv_aplic.h > create mode 100644 include/hw/intc/riscv_imsic.h > > -- > 2.25.1 >
The advanced interrupt architecture (AIA) extends the per-HART local interrupt support. Along with this, it also adds IMSIC (MSI contrllor) and Advanced PLIC (wired interrupt controller). The latest AIA draft specification can be found here: https://github.com/riscv/riscv-aia/releases/download/0.2-draft.27/riscv-interrupts-027.pdf This series adds RISC-V AIA support in QEMU which includes emulating all AIA local CSRs, APLIC, and IMSIC. Only AIA local interrupt filtering is not implemented because we don't have any local interrupt greater than 12. To enable AIA in QEMU, use one of the following: 1) Only AIA local interrupt CSRs: Pass "x-aia=true" as CPU paramenter in the QEMU command-line 2) Only APLIC for virt machine: Pass "aia=aplic" as machine parameter in the QEMU command-line 3) Both APLIC and IMSIC for virt machine: Pass "aia=aplic-imsic" as machine parameter in the QEMU command-line 4) Both APLIC and IMSIC with 2 guest files for virt machine: Pass "aia=aplic-imsic,aia-guests=2" as machine parameter in the QEMU command-line To test series, we require OpenSBI and Linux with AIA support which can be found in riscv_aia_v1 branch at: https://github.com/avpatel/opensbi.git https://github.com/avpatel/linux.git This series can be found riscv_aia_v3 branch at: https://github.com/avpatel/qemu.git Changes since v2: - Update PATCH4 to check and inject interrupt after V=1 when transitioning from V=0 to V=1 Changes since v1: - Revamped whole series and created more granular patches - Added HGEIE and HGEIP CSR emulation for H-extension - Added APLIC emulation - Added IMSIC emulation Anup Patel (22): target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode target/riscv: Implement SGEIP bit in hip and hie CSRs target/riscv: Implement hgeie and hgeip CSRs target/riscv: Improve delivery of guest external interrupts target/riscv: Allow setting CPU feature from machine/device emulation target/riscv: Add AIA cpu feature target/riscv: Add defines for AIA CSRs target/riscv: Allow AIA device emulation to set ireg rmw callback target/riscv: Implement AIA local interrupt priorities target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 target/riscv: Implement AIA hvictl and hviprioX CSRs target/riscv: Implement AIA interrupt filtering CSRs target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs target/riscv: Implement AIA xiselect and xireg CSRs target/riscv: Implement AIA IMSIC interface CSRs hw/riscv: virt: Use AIA INTC compatible string when available target/riscv: Allow users to force enable AIA CSRs in HART hw/intc: Add RISC-V AIA APLIC device emulation hw/riscv: virt: Add optional AIA APLIC support to virt machine hw/intc: Add RISC-V AIA IMSIC device emulation hw/riscv: virt: Add optional AIA IMSIC support to virt machine docs/system: riscv: Document AIA options for virt machine docs/system/riscv/virt.rst | 16 + hw/intc/Kconfig | 6 + hw/intc/meson.build | 2 + hw/intc/riscv_aplic.c | 970 +++++++++++++++++++++++++ hw/intc/riscv_imsic.c | 443 ++++++++++++ hw/riscv/Kconfig | 2 + hw/riscv/virt.c | 694 +++++++++++++++--- include/hw/intc/riscv_aplic.h | 73 ++ include/hw/intc/riscv_imsic.h | 68 ++ include/hw/riscv/virt.h | 40 +- target/riscv/cpu.c | 97 ++- target/riscv/cpu.h | 67 +- target/riscv/cpu_bits.h | 132 ++++ target/riscv/cpu_helper.c | 300 +++++++- target/riscv/csr.c | 1273 ++++++++++++++++++++++++++++++--- target/riscv/machine.c | 24 +- 16 files changed, 3901 insertions(+), 306 deletions(-) create mode 100644 hw/intc/riscv_aplic.c create mode 100644 hw/intc/riscv_imsic.c create mode 100644 include/hw/intc/riscv_aplic.h create mode 100644 include/hw/intc/riscv_imsic.h