| Message ID | 20210123104016.17485-1-bmeng.cn@gmail.com |
|---|---|
| Headers | show |
| Series | hw/riscv: sifive_u: Add missing SPI support | expand |
Hi Bin, On 1/23/21 11:39 AM, Bin Meng wrote: > From: Bin Meng <bin.meng@windriver.com> > > This adds the missing SPI support to the `sifive_u` machine in the QEMU > mainline. With this series, upstream U-Boot for the SiFive HiFive Unleashed > board can boot on QEMU `sifive_u` out of the box. This allows users to > develop and test the recommended RISC-V boot flow with a real world use > case: ZSBL (in QEMU) loads U-Boot SPL from SD card or SPI flash to L2LIM, > then U-Boot SPL loads the payload from SD card or SPI flash that is a > combination of OpenSBI fw_dynamic firmware and U-Boot proper. > > The m25p80 model is updated to support ISSI flash series. A bunch of > ssi-sd issues are fixed, and writing to SD card in SPI mode is supported. > > reST documentation for RISC-V is added. Currently only `sifive_u` > machine is documented, but more to come. > > Changes in v2: > - Mention QPI (Quad Peripheral Interface) mode is not supported > - Add a debug printf in the state handling codes > - Fix several typos in the commit message > - new patch: add a state representing Nac > - Make this fix a separate patch from the CMD18 support > - Fix 2 typos in the commit message > - Add a comment block to explain the CMD12 timing > - Catch CMD12 in all of the data read states per the timing requirement > - Move multiple write token definitions out of this patch > - Correct the "coding" typo in the commit message > - Correct the "token" typo in the commit message > - Add 'write_bytes' in vmstate_ssi_sd > - Correct the "token" typo in the commit message > - Introduce multiple write token definitions in this patch > - new patch: bump up version ids of VMStateDescription > - Log guest error when trying to write reserved registers > - Log guest error when trying to access out-of-bounds registers > - log guest error when writing to reserved bits for chip select > registers and watermark registers > - Log unimplemented warning when trying to write direct-map flash > interface registers > - Add test tx fifo full logic in sifive_spi_read(), hence remove > setting the tx fifo full flag in sifive_spi_write(). > - Populate register with their default value > - Correct the "connects" typo in the commit message > - Mention in the commit message that <reg> property does not populate > the second group which represents the memory mapped address of the > SPI flash > - Correct the "connects" typo in the commit message > - Correct several typos in sifive_u.rst > - Update doc to mention U-Boot v2021.01 > > Bin Meng (25): > hw/block: m25p80: Add ISSI SPI flash support > hw/block: m25p80: Add various ISSI flash information > hw/sd: ssi-sd: Fix incorrect card response sequence > hw/sd: sd: Support CMD59 for SPI mode > hw/sd: sd: Drop sd_crc16() > util: Add CRC16 (CCITT) calculation routines > hw/sd: ssi-sd: Suffix a data block with CRC16 > hw/sd: ssi-sd: Add a state representing Nac > hw/sd: ssi-sd: Fix the wrong command index for STOP_TRANSMISSION > hw/sd: ssi-sd: Support multiple block read > hw/sd: ssi-sd: Use macros for the dummy value and tokens in the > transfer > hw/sd: sd: Remove duplicated codes in single/multiple block read/write > hw/sd: sd: Allow single/multiple block write for SPI mode > hw/sd: sd.h: Cosmetic change of using spaces > hw/sd: Introduce receive_ready() callback > hw/sd: ssi-sd: Support single block write > hw/sd: ssi-sd: Support multiple block write > hw/sd: ssi-sd: Bump up version ids of VMStateDescription > hw/ssi: Add SiFive SPI controller support > hw/riscv: sifive_u: Add QSPI0 controller and connect a flash > hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card > hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value > docs/system: Sort targets in alphabetical order > docs/system: Add RISC-V documentation > docs/system: riscv: Add documentation for sifive_u machine I'm queuing patches 3-9,11,14 to sd-next, and will repost your 10,12,13,15-18 based on it. Regards, Phil.
From: Bin Meng <bin.meng@windriver.com> This adds the missing SPI support to the `sifive_u` machine in the QEMU mainline. With this series, upstream U-Boot for the SiFive HiFive Unleashed board can boot on QEMU `sifive_u` out of the box. This allows users to develop and test the recommended RISC-V boot flow with a real world use case: ZSBL (in QEMU) loads U-Boot SPL from SD card or SPI flash to L2LIM, then U-Boot SPL loads the payload from SD card or SPI flash that is a combination of OpenSBI fw_dynamic firmware and U-Boot proper. The m25p80 model is updated to support ISSI flash series. A bunch of ssi-sd issues are fixed, and writing to SD card in SPI mode is supported. reST documentation for RISC-V is added. Currently only `sifive_u` machine is documented, but more to come. Changes in v2: - Mention QPI (Quad Peripheral Interface) mode is not supported - Add a debug printf in the state handling codes - Fix several typos in the commit message - new patch: add a state representing Nac - Make this fix a separate patch from the CMD18 support - Fix 2 typos in the commit message - Add a comment block to explain the CMD12 timing - Catch CMD12 in all of the data read states per the timing requirement - Move multiple write token definitions out of this patch - Correct the "coding" typo in the commit message - Correct the "token" typo in the commit message - Add 'write_bytes' in vmstate_ssi_sd - Correct the "token" typo in the commit message - Introduce multiple write token definitions in this patch - new patch: bump up version ids of VMStateDescription - Log guest error when trying to write reserved registers - Log guest error when trying to access out-of-bounds registers - log guest error when writing to reserved bits for chip select registers and watermark registers - Log unimplemented warning when trying to write direct-map flash interface registers - Add test tx fifo full logic in sifive_spi_read(), hence remove setting the tx fifo full flag in sifive_spi_write(). - Populate register with their default value - Correct the "connects" typo in the commit message - Mention in the commit message that <reg> property does not populate the second group which represents the memory mapped address of the SPI flash - Correct the "connects" typo in the commit message - Correct several typos in sifive_u.rst - Update doc to mention U-Boot v2021.01 Bin Meng (25): hw/block: m25p80: Add ISSI SPI flash support hw/block: m25p80: Add various ISSI flash information hw/sd: ssi-sd: Fix incorrect card response sequence hw/sd: sd: Support CMD59 for SPI mode hw/sd: sd: Drop sd_crc16() util: Add CRC16 (CCITT) calculation routines hw/sd: ssi-sd: Suffix a data block with CRC16 hw/sd: ssi-sd: Add a state representing Nac hw/sd: ssi-sd: Fix the wrong command index for STOP_TRANSMISSION hw/sd: ssi-sd: Support multiple block read hw/sd: ssi-sd: Use macros for the dummy value and tokens in the transfer hw/sd: sd: Remove duplicated codes in single/multiple block read/write hw/sd: sd: Allow single/multiple block write for SPI mode hw/sd: sd.h: Cosmetic change of using spaces hw/sd: Introduce receive_ready() callback hw/sd: ssi-sd: Support single block write hw/sd: ssi-sd: Support multiple block write hw/sd: ssi-sd: Bump up version ids of VMStateDescription hw/ssi: Add SiFive SPI controller support hw/riscv: sifive_u: Add QSPI0 controller and connect a flash hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value docs/system: Sort targets in alphabetical order docs/system: Add RISC-V documentation docs/system: riscv: Add documentation for sifive_u machine docs/system/riscv/sifive_u.rst | 336 ++++++++++++++++++++++++++++++ docs/system/target-riscv.rst | 72 +++++++ docs/system/targets.rst | 20 +- include/hw/riscv/sifive_u.h | 9 +- include/hw/sd/sd.h | 44 ++-- include/hw/ssi/sifive_spi.h | 47 +++++ include/qemu/crc-ccitt.h | 33 +++ hw/block/m25p80.c | 57 ++++- hw/riscv/sifive_u.c | 91 ++++++++ hw/sd/core.c | 13 ++ hw/sd/sd.c | 82 +------- hw/sd/ssi-sd.c | 166 +++++++++++++-- hw/ssi/sifive_spi.c | 367 +++++++++++++++++++++++++++++++++ util/crc-ccitt.c | 127 ++++++++++++ hw/riscv/Kconfig | 3 + hw/ssi/Kconfig | 4 + hw/ssi/meson.build | 1 + util/meson.build | 1 + 18 files changed, 1347 insertions(+), 126 deletions(-) create mode 100644 docs/system/riscv/sifive_u.rst create mode 100644 docs/system/target-riscv.rst create mode 100644 include/hw/ssi/sifive_spi.h create mode 100644 include/qemu/crc-ccitt.h create mode 100644 hw/ssi/sifive_spi.c create mode 100644 util/crc-ccitt.c