From patchwork Tue May 8 17:31:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 910355 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="or/OEmoa"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40gRQf1gmXz9s27 for ; Wed, 9 May 2018 03:32:56 +1000 (AEST) Received: from localhost ([::1]:52549 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fG6Tt-00083B-A7 for incoming@patchwork.ozlabs.org; Tue, 08 May 2018 13:32:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43786) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fG6T2-00081W-37 for qemu-devel@nongnu.org; Tue, 08 May 2018 13:32:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fG6Sy-0005FE-VU for qemu-devel@nongnu.org; Tue, 08 May 2018 13:32:00 -0400 Received: from mail-lf0-x243.google.com ([2a00:1450:4010:c07::243]:38800) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fG6Sy-0005Ef-NO for qemu-devel@nongnu.org; Tue, 08 May 2018 13:31:56 -0400 Received: by mail-lf0-x243.google.com with SMTP id z142-v6so3769823lff.5 for ; Tue, 08 May 2018 10:31:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=ldMRu9xJVxaFiFgWbEDlOwjSl+1no1KGWBm2HJMqm+U=; b=or/OEmoauL3mI+SE0rtB477mehdq/U7YbBFOhkuXDY3zYyOJyTF0h2xdXUU+JdwryS 5f8bceiOvOwG8uewXaeBFWxaBYAv34RlA28J62pW4epD+TQKW/KXdsEgGy8peRLblvjD KM1khnpbrHqRdSBwFQGVyN1bRirU8MjhrB56c/YcEIZ+bHnowV0PqiPyEFXvbb8hkPLT +nti/F0InO+Lj0P1+8p/ccmFr8J0KLvq2UpoeMXFxySukgZZWg2tABXxuc52HkjjT8zD QI4cmvQmvw8RvgMuwqjYgNRY8D5du0aEXbOvIIiOEJtLPdUVE6hpF08KlGRhrA4DNYs9 mnfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=ldMRu9xJVxaFiFgWbEDlOwjSl+1no1KGWBm2HJMqm+U=; b=cwR6m502+esI4uVKEBskfUh1hm2bznAATag1R5K6RnE9nvXhwZFUnjOXxwMIh/nIHC AkgMpS1K6XXHIELRSS8KFAcMtxiQ41NnRlEqcVzxJApbZA/e/uiPTYqnU7j+0kOjTpvu bCNUgKrvWmTQ+tRBJWKzjIftrgAGbL9j3h9IHPwFXFQQhHTu9jtW0yFwRqbHPqLNqyNm qQ/sGqU4M+8uCZUlULi376GrqpiRrN0tEOU5sfm/T8qIMQ3fSmo/LD1VOwfjpRW2VFMT DM3HngUmwVdJ3NJHq7l3YCubKAz/EEVHz1J4o3vZWAUn4a/xJ56iQxx0G/fXlAz/lr4Y A16Q== X-Gm-Message-State: ALQs6tCfW8hBcB3/HqRnQFGoTlYukPUfaYhy63plwn+ehCaoSf3cYwx4 9efWS+wN2RC+ylGcxH+A3vtFsA== X-Google-Smtp-Source: AB8JxZoZ3icSJKO2YYgcN4TbHKgLWtQBM2azBR0EDdcb0HgbwoY3mbonF7OPlxHyvQ2jvd1tY5J35g== X-Received: by 2002:a2e:9756:: with SMTP id f22-v6mr22725943ljj.111.1525800714812; Tue, 08 May 2018 10:31:54 -0700 (PDT) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id o18-v6sm5361801lfg.16.2018.05.08.10.31.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 May 2018 10:31:53 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 8 May 2018 19:31:16 +0200 Message-Id: <20180508173152.29327-1-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PATCH v2 00/36] target-microblaze: Add support for Extended Addressing X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, frederic.konrad@adacore.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" This series adds support for Extended Addressing to our MicroBlaze models. It adds both the non-MMU load/store EA and the extended MMU addressing. There are several ways to implement this but since there are further 64-bit extensions in the pipe, I've chosen to convert the cpu_SR special regs to 64-bit. Both non-EA and EA enabled cores run out of the same build with TARGET_LONG_BITS=64. Patches 30 - 36 are new patches cleaning up code suggested during review. Comments? Thanks & Best regards, Edgar ChangeLog: v1 -> v2: * Add patch to simplify address computation using tcg_gen_addi_i32() * Add patches to cleanup eval_cond_jmp using tcg_gen_movcond_i32() * Add patch to cleanup microblaze MMU logs * Correct trap_userspace() usage when adding Extended Addressing * Correct name for special register sr13 to redr Edgar E. Iglesias (36): target-microblaze: dec_load: Use bool instead of unsigned int target-microblaze: dec_store: Use bool instead of unsigned int target-microblaze: compute_ldst_addr: Use bool instead of int target-microblaze: Fallback to our latest CPU version target-microblaze: Correct special register array sizes target-microblaze: Correct the PVR array size target-microblaze: Tighten up TCGv_i32 vs TCGv type usage target-microblaze: Remove USE_MMU PVR checks target-microblaze: Conditionalize setting of PVR11_USE_MMU target-microblaze: Bypass MMU with MMU_NOMMU_IDX target-microblaze: Make compute_ldst_addr always use a temp target-microblaze: Remove pointer indirection for ld/st addresses target-microblaze: Use TCGv for load/store addresses target-microblaze: Name special registers we support target-microblaze: Break out trap_userspace() target-microblaze: Break out trap_illegal() target-microblaze: dec_msr: Use bool and extract32 target-microblaze: dec_msr: Reuse more code when reg-decoding target-microblaze: dec_msr: Fix MTS to FSR target-microblaze: Make special registers 64-bit target-microblaze: Setup for 64bit addressing target-microblaze: Add Extended Addressing target-microblaze: Implement MFSE EAR target-microblaze: mmu: Add R_TBLX_MISS macros target-microblaze: mmu: Remove unused register state target-microblaze: mmu: Prepare for 64-bit addresses target-microblaze: mmu: Add a configurable output address mask target-microblaze: Add support for extended access to TLBLO target-microblaze: Allow address sizes between 32 and 64 bits target-microblaze: Simplify address computation using tcg_gen_addi_i32() target-microblaze: mmu: Cleanup debug log messages target-microblaze: Use table based condition-codes conversion target-microblaze: Remove argument b in eval_cc() target-microblaze: Convert env_btaken to i64 target-microblaze: Convert env_btarget to i64 target-microblaze: Use tcg_gen_movcond in eval_cond_jmp configure | 1 + linux-user/microblaze/cpu_loop.c | 4 +- target/microblaze/cpu.c | 30 +- target/microblaze/cpu.h | 20 +- target/microblaze/helper.c | 30 +- target/microblaze/helper.h | 8 +- target/microblaze/mmu.c | 81 ++-- target/microblaze/mmu.h | 17 +- target/microblaze/op_helper.c | 31 +- target/microblaze/translate.c | 926 +++++++++++++++++++-------------------- 10 files changed, 585 insertions(+), 563 deletions(-) Reviewed-by: Richard Henderson