| Message ID | 20180808120133.32604-1-npiggin@gmail.com |
|---|---|
| State | Accepted |
| Headers | show |
| Series | [v2] libpdbg/p9chip: use SPWKUP_FSP instead of SPWKUP_OTR | expand |
| Context | Check | Description |
|---|---|---|
| snowpatch_ozlabs/apply_patch | success | master/apply_patch Successfully applied |
| snowpatch_ozlabs/build-multiarch | success | Test build-multiarch on branch master |
On 08/08/2018 05:31 PM, Nicholas Piggin wrote: > Dean Sanner notes that pdbg should not use the OTR special wakeup > register, as it is used by the PM complex (i.e., SGPE, CME, PGPE). > It should use the FSP register instead, which is reserved for service > processor firmware, and nothing else in OpenBMC uses this at the > moment. > > In theory when pdbg is used via the host, it should be using the HYP > register via some OPAL arbitration mechanism (OPAL being the owner of > the HYP register), but in the absence of any of that mechanism, FSP > is the best option. > > Cc: Dean Sanner <dsanner@us.ibm.com> > Cc: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Looks good to me. Reviewed-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Thanks, -Mahesh. > --- > libpdbg/p9chip.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/libpdbg/p9chip.c b/libpdbg/p9chip.c > index c43b0cc..1433d19 100644 > --- a/libpdbg/p9chip.c > +++ b/libpdbg/p9chip.c > @@ -71,8 +71,8 @@ > #define NET_CTRL0_FENCE_EN PPC_BIT(18) > #define NET_CTRL0_WOR 0xf0042 > #define PPM_GPMMR 0xf0100 > -#define PPM_SPWKUP_OTR 0xf010a > -#define PPM_SSHOTR 0xf0113 > +#define PPM_SPWKUP_FSP 0xf010b > +#define PPM_SSHFSP 0xf0111 > #define SPECIAL_WKUP_DONE PPC_BIT(1) > > #define RAS_STATUS_TIMEOUT 100 /* 100ms */ > @@ -478,10 +478,10 @@ static int p9_core_probe(struct pdbg_target *target) > if (!(value & NET_CTRL0_CHIPLET_ENABLE)) > return -1; > > - CHECK_ERR(pib_write(target, PPM_SPWKUP_OTR, PPC_BIT(0))); > + CHECK_ERR(pib_write(target, PPM_SPWKUP_FSP, PPC_BIT(0))); > do { > usleep(1000); > - CHECK_ERR(pib_read(target, PPM_SSHOTR, &value)); > + CHECK_ERR(pib_read(target, PPM_SSHFSP, &value)); > > if (i++ > SPECIAL_WKUP_TIMEOUT) { > PR_ERROR("Timeout waiting for special wakeup on %s@0x%08" PRIx64 "\n", target->name, > @@ -496,7 +496,7 @@ static int p9_core_probe(struct pdbg_target *target) > static void p9_core_release(struct pdbg_target *target) > { > usleep(1); /* enforce small delay before and after it is cleared */ > - pib_write(target, PPM_SPWKUP_OTR, 0); > + pib_write(target, PPM_SPWKUP_FSP, 0); > usleep(10000); > } >
diff --git a/libpdbg/p9chip.c b/libpdbg/p9chip.c index c43b0cc..1433d19 100644 --- a/libpdbg/p9chip.c +++ b/libpdbg/p9chip.c @@ -71,8 +71,8 @@ #define NET_CTRL0_FENCE_EN PPC_BIT(18) #define NET_CTRL0_WOR 0xf0042 #define PPM_GPMMR 0xf0100 -#define PPM_SPWKUP_OTR 0xf010a -#define PPM_SSHOTR 0xf0113 +#define PPM_SPWKUP_FSP 0xf010b +#define PPM_SSHFSP 0xf0111 #define SPECIAL_WKUP_DONE PPC_BIT(1) #define RAS_STATUS_TIMEOUT 100 /* 100ms */ @@ -478,10 +478,10 @@ static int p9_core_probe(struct pdbg_target *target) if (!(value & NET_CTRL0_CHIPLET_ENABLE)) return -1; - CHECK_ERR(pib_write(target, PPM_SPWKUP_OTR, PPC_BIT(0))); + CHECK_ERR(pib_write(target, PPM_SPWKUP_FSP, PPC_BIT(0))); do { usleep(1000); - CHECK_ERR(pib_read(target, PPM_SSHOTR, &value)); + CHECK_ERR(pib_read(target, PPM_SSHFSP, &value)); if (i++ > SPECIAL_WKUP_TIMEOUT) { PR_ERROR("Timeout waiting for special wakeup on %s@0x%08" PRIx64 "\n", target->name, @@ -496,7 +496,7 @@ static int p9_core_probe(struct pdbg_target *target) static void p9_core_release(struct pdbg_target *target) { usleep(1); /* enforce small delay before and after it is cleared */ - pib_write(target, PPM_SPWKUP_OTR, 0); + pib_write(target, PPM_SPWKUP_FSP, 0); usleep(10000); }
Dean Sanner notes that pdbg should not use the OTR special wakeup register, as it is used by the PM complex (i.e., SGPE, CME, PGPE). It should use the FSP register instead, which is reserved for service processor firmware, and nothing else in OpenBMC uses this at the moment. In theory when pdbg is used via the host, it should be using the HYP register via some OPAL arbitration mechanism (OPAL being the owner of the HYP register), but in the absence of any of that mechanism, FSP is the best option. Cc: Dean Sanner <dsanner@us.ibm.com> Cc: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> --- libpdbg/p9chip.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)