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[OpenWrt-Devel,v2,1/3] ar71xx: fix ethernet initialization on QCA953x-based boards (TP-Link TL-WR841N/ND v9, Compex WPJ531)

Message ID c727813bc7772e91fa69019575a9a548a85cd6d0.1436230659.git.mschiffer@universe-factory.net
State Accepted
Headers show

Commit Message

Matthias Schiffer July 7, 2015, 12:59 a.m. UTC 
The initialization routines for these boards were relying on some (wrong)
defaults for the QCA953x ethernet. Make these defaults explicit to prevent
breaking them when the QCA953x defaults are fixed.

Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
---
 target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c | 6 ++++++
 target/linux/ar71xx/files/arch/mips/ath79/mach-wpj531.c       | 7 +++++++
 2 files changed, 13 insertions(+)
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Patch

diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c
index c28afc6..3e5c2a2 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c
@@ -109,12 +109,18 @@  static void __init tl_ap143_setup(void)
 	ath79_register_mdio(0, 0x0);
 
 	/* LAN */
+	ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
+	ath79_eth1_data.duplex = DUPLEX_FULL;
+	ath79_switch_data.phy_poll_mask |= BIT(4);
 	ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
 	ath79_register_eth(1);
 
 	/* WAN */
 	ath79_switch_data.phy4_mii_en = 1;
 	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
+	ath79_eth0_data.duplex = DUPLEX_FULL;
+	ath79_eth0_data.speed = SPEED_100;
+	ath79_eth0_data.phy_mask = BIT(4);
 	ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
 	ath79_register_eth(0);
 
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj531.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj531.c
index bc13d70..e665a2e 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj531.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj531.c
@@ -105,12 +105,19 @@  static void __init common_setup(void)
 	ath79_register_mdio(0, 0x0);
 
 	/* LAN */
+	ath79_eth0_data.duplex = DUPLEX_FULL;
+	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
+	ath79_eth0_data.speed = SPEED_100;
+	ath79_eth0_data.phy_mask = BIT(4);
 	ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
 	ath79_register_eth(0);
 
 	/* WAN */
 	ath79_switch_data.phy4_mii_en = 1;
+	ath79_eth1_data.duplex = DUPLEX_FULL;
 	ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
+	ath79_eth1_data.speed = SPEED_100;
+	ath79_switch_data.phy_poll_mask |= BIT(4);
 	ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
 	ath79_register_eth(1);