From patchwork Thu Sep 17 12:38:01 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris X-Patchwork-Id: 518825 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from arrakis.dune.hu (arrakis.dune.hu [78.24.191.176]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id A077F140297 for ; Thu, 17 Sep 2015 22:38:21 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=WhQS3xUX; dkim-atps=neutral Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id 1CB73289C79; Thu, 17 Sep 2015 14:36:59 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on arrakis.dune.hu X-Spam-Level: X-Spam-Status: No, score=-1.2 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, HTML_MESSAGE, T_DKIM_INVALID autolearn=no version=3.3.2 Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id 9B2512807DB for ; Thu, 17 Sep 2015 14:36:53 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 CL_IP_EQ_HELO_IP=-2 (check from: .gmail. - helo: .mail-vk0-f66.google. - helo-domain: .google.) FROM/MX_MATCHES_HELO(DOMAIN)=-2; rate: -8.5 Received: from mail-vk0-f66.google.com (mail-vk0-f66.google.com [209.85.213.66]) by arrakis.dune.hu (Postfix) with ESMTPS for ; Thu, 17 Sep 2015 14:36:53 +0200 (CEST) Received: by vkao3 with SMTP id o3so929222vka.2 for ; Thu, 17 Sep 2015 05:38:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:date:message-id:subject:from:to:content-type; bh=NFf/LsayB7Iu3Cszab4rmJo6YMszLwijNjGNd9tgP/E=; b=WhQS3xUX4WA2PN2ARBPBjatAt674vMHdbYWJwER+gJovC3VSdovmMii2sWiJ1E0piK Eem/Xiu1Z9sR7XKFL2gkmtFGU2X5YR259EbStql0VpEY6Upc11XfPK/yUth/qH6p4hJJ A1OSjb+eLtk3f3fgGS/EORkD79T7LXsTuildnFXUbe/s6ozW5shC4nTxyKQB2ZNEFYWL O1hCuCScUaYWuOBmogG9mampNu4qVHTvY6d6VYC/owXPfD09kiJ8zKSusdnhUimPJdRc j5o/98HHkJSXdZMqC1GPzAYWa4wS5XzglX4V48MjsjZcj5OdTO4N656g3VRnWWLECqUA 7cHQ== MIME-Version: 1.0 X-Received: by 10.31.52.140 with SMTP id b134mr32850132vka.136.1442493481946; Thu, 17 Sep 2015 05:38:01 -0700 (PDT) Received: by 10.31.77.6 with HTTP; Thu, 17 Sep 2015 05:38:01 -0700 (PDT) Date: Thu, 17 Sep 2015 07:38:01 -0500 Message-ID: From: Chris Blake To: openwrt-devel@lists.openwrt.org Subject: [OpenWrt-Devel] [PATCH] ar71xx: add support for qca955x sgmii/serdes calibration X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: openwrt-devel-bounces@lists.openwrt.org Sender: "openwrt-devel" This patch is to add support for sgmii/serdes calibration from within the OpenWRT environment. This is needed on boards that do not use u-boot or do not have a pre-init process that runs calibration. Signed-off-by: Chris R Blake --- --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h 2015-08-05 12:58:15.580496899 +0200 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h 2015-08-05 13:52:32.590857293 +0200 @@ -360,6 +360,7 @@ #define QCA955X_PLL_CLK_CTRL_REG 0x08 #define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28 #define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48 +#define QCA955X_PLL_ETH_SGMII_SERDES_REG 0x4c #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f @@ -392,6 +393,10 @@ #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) +#define QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT BIT(2) +#define QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK BIT(1) +#define QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL BIT(0) + #define QCA956X_PLL_CPU_CONFIG_REG 0x00 #define QCA956X_PLL_CPU_CONFIG1_REG 0x04 #define QCA956X_PLL_DDR_CONFIG_REG 0x08 @@ -1104,5 +1109,11 @@ #define QCA955X_ETH_CFG_RDV_DELAY BIT(16) #define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3 #define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16 + +#define QCA955X_GMAC_REG_SGMII_SERDES 0x0018 +#define QCA955X_SGMII_SERDES_RES_CALIBRATION BIT(23) +#define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf +#define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23 +#define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15) #endif /* __ASM_MACH_AR71XX_REGS_H */ --- a/arch/mips/ath79/dev-eth.c 2015-08-05 14:17:25.757504251 +0200 +++ b/arch/mips/ath79/dev-eth.c 2015-08-05 14:09:54.716333554 +0200 @@ -849,6 +849,37 @@ void __init ath79_setup_qca955x_eth_rx_d iounmap(base); } +void __init ath79_setup_qca955x_eth_serdes_cal(unsigned int sgmii_value) +{ + void __iomem *ethbase, *pllbase; + u32 t; + + ethbase = ioremap_nocache(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE); + pllbase = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); + + /* To Check the locking of the SGMII PLL */ + t = __raw_readl(ethbase + QCA955X_GMAC_REG_SGMII_SERDES); + t &= ~(QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK << + QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT); + t |= (sgmii_value & QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK) << + QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT; + __raw_writel(t, ethbase + QCA955X_GMAC_REG_SGMII_SERDES); + + __raw_writel(QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT | + QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK | + QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL, + pllbase + QCA955X_PLL_ETH_SGMII_SERDES_REG); + + ath79_device_reset_clear(QCA955X_RESET_SGMII_ANALOG); + ath79_device_reset_clear(QCA955X_RESET_SGMII); + + while (!(__raw_readl(ethbase + QCA955X_GMAC_REG_SGMII_SERDES) & + QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS)); + + iounmap(ethbase); + iounmap(pllbase); +} + static int ath79_eth_instance __initdata; void __init ath79_register_eth(unsigned int id) { --- a/arch/mips/ath79/dev-eth.h 2015-08-05 14:17:25.757504251 +0200 +++ b/arch/mips/ath79/dev-eth.h 2015-08-05 13:58:20.292866210 +0200 @@ -50,5 +50,6 @@ void ath79_setup_ar934x_eth_cfg(u32 mask void ath79_setup_ar934x_eth_rx_delay(unsigned int rxd, unsigned int rxdv); void ath79_setup_qca955x_eth_cfg(u32 mask); void ath79_setup_qca955x_eth_rx_delay(unsigned int rxd, unsigned int rxdv); +void ath79_setup_qca955x_eth_serdes_cal(unsigned int sgmii_value); #endif /* _ATH79_DEV_ETH_H */