From patchwork Sun Nov 29 22:00:02 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Philippe DUCHEIN X-Patchwork-Id: 549823 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from arrakis.dune.hu (arrakis.dune.hu [78.24.191.176]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 7D5D81402A5 for ; Mon, 30 Nov 2015 09:00:49 +1100 (AEDT) Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id 8368828C672; Sun, 29 Nov 2015 23:00:14 +0100 (CET) Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id B019E28C66D for ; Sun, 29 Nov 2015 23:00:10 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 CL_IP_EQ_FROM_MX=-3.1; rate: -7.6 Received: from zimbra.duchein.net (246.111.88.91.rev.sfr.net [91.88.111.246]) by arrakis.dune.hu (Postfix) with ESMTPS for ; Sun, 29 Nov 2015 23:00:09 +0100 (CET) Received: from localhost (localhost.localdomain [127.0.0.1]) by zimbra.duchein.net (Postfix) with ESMTP id 3B39B1EC010B; Sun, 29 Nov 2015 23:00:12 +0100 (CET) Received: from zimbra.duchein.net ([127.0.0.1]) by localhost (zimbra.duchein.net [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id IQ_YycWLFM9w; Sun, 29 Nov 2015 23:00:04 +0100 (CET) Received: from localhost (localhost.localdomain [127.0.0.1]) by zimbra.duchein.net (Postfix) with ESMTP id 6FB121EC0616; Sun, 29 Nov 2015 23:00:01 +0100 (CET) X-Virus-Scanned: amavisd-new at duchein.net Received: from zimbra.duchein.net ([127.0.0.1]) by localhost (zimbra.duchein.net [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id ASKQ-o-zBSxk; Sun, 29 Nov 2015 23:00:01 +0100 (CET) Received: from imacdephilippe.lan (241.111.88.91.rev.sfr.net [91.88.111.241]) by zimbra.duchein.net (Postfix) with ESMTPSA id CD2291EC010B; Sun, 29 Nov 2015 23:00:00 +0100 (CET) Mime-Version: 1.0 (Mac OS X Mail 9.1 \(3096.5\)) From: Philippe DUCHEIN In-Reply-To: <5650D52B.9020600@openwrt.org> Date: Sun, 29 Nov 2015 23:00:02 +0100 Message-Id: References: <86F9C0C7-4317-4261-A54F-343634BFBCB0@duchein.net> <5650B07D.1080102@openwrt.org> <5650D52B.9020600@openwrt.org> To: John Crispin X-Mailer: Apple Mail (2.3096.5) Cc: openwrt-devel@lists.openwrt.org Subject: Re: [OpenWrt-Devel] [PATCH v2] ar71xx: Add support for Wallys DR344 X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: openwrt-devel-bounces@lists.openwrt.org Sender: "openwrt-devel" Hi John, maybe i wrote it one month ago and trunk release change too much So i rewrite it and checked it on r47670 pduchein@compilation:~/compilation/bs/dr344$ git clone git://git.openwrt.org/openwrt.git Cloning into 'openwrt'... remote: Counting objects: 327146, done. remote: Compressing objects: 100% (92388/92388), done. remote: Total 327146 (delta 225104), reused 320595 (delta 220502) Receiving objects: 100% (327146/327146), 114.20 MiB | 10.78 MiB/s, done. Resolving deltas: 100% (225104/225104), done. pduchein@compilation:~/compilation/bs/dr344$ cd openwrt/ pduchein@compilation:~/compilation/bs/dr344/openwrt$ patch -p1 < ../dr344.patch patching file target/linux/ar71xx/base-files/etc/diag.sh Hunk #1 succeeded at 95 (offset 3 lines). patching file target/linux/ar71xx/base-files/etc/board.d/02_network Hunk #1 succeeded at 16 (offset -1 lines). patching file target/linux/ar71xx/base-files/lib/ar71xx.sh Hunk #1 succeeded at 463 (offset 7 lines). patching file target/linux/ar71xx/base-files/lib/upgrade/platform.sh Hunk #1 succeeded at 184 (offset 1 line). patching file target/linux/ar71xx/config-4.1 Hunk #1 succeeded at 66 (offset 2 lines). patching file target/linux/ar71xx/generic/profiles/wallys.mk patching file target/linux/ar71xx/image/Makefile Hunk #1 succeeded at 1502 (offset 45 lines). Hunk #2 succeeded at 2276 with fuzz 1 (offset -18 lines). patching file target/linux/ar71xx/patches-4.1/702-MIPS-ath79-openwrt-dr344.patch patching file target/linux/ar71xx/files/arch/mips/ath79/mach-dr344.c pduchein@compilation:~/compilation/bs/dr344/openwrt$ This patch is for Wallys DR344 support under OpenWRT. It’s release 2.2 Changelog: updated to support r47670 trunk release Signed-off-by: Philippe DUCHEIN > — > Le 21 nov. 2015 à 21:33, John Crispin a écrit : > > Hi, > > Applying: ar71xx: Add support for Wallys DR344 > fatal: sha1 information is lacking or useless > (target/linux/ar71xx/base-files/etc/diag.sh). > Repository lacks necessary blobs to fall back on 3-way merge. > Cannot fall back to three-way merge. > Patch failed at 0001 ar71xx: Add support for Wallys DR344 > When you have resolved this problem run "git am --resolved". > If you would prefer to skip this patch, instead run "git am --skip". > To restore the original branch and stop patching run "git am --abort". > applying 547222 FAILED > > which tree are you basing this on ? > > John > > On 21/11/2015 19:56, Philippe DUCHEIN wrote: >> Hi John, >> Sorry for convenience >> I suppressed it >> >> -------------------------------- >> >> This patch is for Wallys DR344 support under OpenWRT. It’s release 2.1 >> ChangeLog: suppress suppress blank line insert >> into target/linux/ar71xx/image/Makefile b/target/linux/ar71xx/image/Makefile >> >> Signed-off-by: Philippe DUCHEIN >> >> >> >> --- >> >> diff -Nru a/target/linux/ar71xx/base-files/etc/diag.sh >> b/target/linux/ar71xx/base-files/etc/diag.sh >> --- a/target/linux/ar71xx/base-files/etc/diag.sh2015-10-27 >> 18:57:41.368735097 +0100 >> +++ b/target/linux/ar71xx/base-files/etc/diag.sh2015-10-29 >> 12:05:58.995324966 +0100 >> @@ -92,6 +92,9 @@ >> dlan-pro-1200-ac) >> status_led="devolo:status:wlan" >> ;; >> +dr344) >> +status_led="dr344:green:status" >> +;; >> dragino2) >> status_led="dragino2:red:system" >> ;; >> diff -Nru a/target/linux/ar71xx/base-files/etc/uci-defaults/02_network >> b/target/linux/ar71xx/base-files/etc/uci-defaults/02_network >> --- >> a/target/linux/ar71xx/base-files/etc/uci-defaults/02_network2015-10-27 >> 18:57:41.363735040 +0100 >> +++ >> b/target/linux/ar71xx/base-files/etc/uci-defaults/02_network2015-10-29 >> 12:05:58.995324966 +0100 >> @@ -17,6 +17,7 @@ >> case "$board" in >> all0315n |\ >> all0258n |\ >> +dr344 |\ >> ja76pf2|\ >> rocket-m-ti |\ >> ubnt-unifi-outdoor) >> diff -Nru a/target/linux/ar71xx/base-files/lib/ar71xx.sh >> b/target/linux/ar71xx/base-files/lib/ar71xx.sh >> --- a/target/linux/ar71xx/base-files/lib/ar71xx.sh2015-10-27 >> 18:57:41.341734786 +0100 >> +++ b/target/linux/ar71xx/base-files/lib/ar71xx.sh2015-10-29 >> 12:05:58.996324978 +0100 >> @@ -456,6 +456,9 @@ >> *"dLAN pro 1200+ WiFi ac") >> name="dlan-pro-1200-ac" >> ;; >> +*DR344) >> +name="dr344" >> +;; >> *"Dragino v2") >> name="dragino2" >> ;; >> diff -Nru a/target/linux/ar71xx/base-files/lib/upgrade/platform.sh >> b/target/linux/ar71xx/base-files/lib/upgrade/platform.sh >> --- a/target/linux/ar71xx/base-files/lib/upgrade/platform.sh2015-10-27 >> 18:57:41.329734649 +0100 >> +++ b/target/linux/ar71xx/base-files/lib/upgrade/platform.sh2015-10-29 >> 12:06:23.597611781 +0100 >> @@ -183,6 +183,7 @@ >> ap96 | \ >> bxu2000n-2-a1 | \ >> db120 | \ >> +dr344 | \ >> f9k1115v2 |\ >> hornet-ub | \ >> mr12 | \ >> diff -Nru a/target/linux/ar71xx/config-4.1 b/target/linux/ar71xx/config-4.1 >> --- a/target/linux/ar71xx/config-4.12015-10-27 18:57:41.379735223 +0100 >> +++ b/target/linux/ar71xx/config-4.12015-10-29 12:05:58.996324978 +0100 >> @@ -64,6 +64,7 @@ >> CONFIG_ATH79_MACH_DIR_825_C1=y >> CONFIG_ATH79_MACH_DLAN_PRO_1200_AC=y >> CONFIG_ATH79_MACH_DLAN_PRO_500_WP=y >> +CONFIG_ATH79_MACH_DR344=y >> CONFIG_ATH79_MACH_DRAGINO2=y >> CONFIG_ATH79_MACH_EAP300V2=y >> CONFIG_ATH79_MACH_EAP7660D=y >> diff -Nru a/target/linux/ar71xx/generic/profiles/wallys.mk >> b/target/linux/ar71xx/generic/profiles/wallys.mk >> --- a/target/linux/ar71xx/generic/profiles/wallys.mk1970-01-01 >> 01:00:00.000000000 +0100 >> +++ b/target/linux/ar71xx/generic/profiles/wallys.mk2015-10-29 >> 12:05:58.996324978 +0100 >> @@ -0,0 +1,17 @@ >> +# >> +# Copyright (C) 2015 Philippe DUCHEIN > >> >> +# Copyright (C) 2009 OpenWrt.org > >> +# This is free software, licensed under the GNU General Public License v2. >> +# See /LICENSE for more information. >> +# >> + >> +define Profile/DR344 >> +NAME:=Wallys DR344 >> +endef >> + >> +define Profile/DR344/Description >> +Package set optimized for the Wallys DR344 board. >> +endef >> + >> +$(eval $(call Profile,DR344)) >> + >> diff -Nru a/target/linux/ar71xx/image/Makefile >> b/target/linux/ar71xx/image/Makefile >> --- a/target/linux/ar71xx/image/Makefile2015-10-27 18:57:41.248733718 +0100 >> +++ b/target/linux/ar71xx/image/Makefile2015-10-29 12:05:58.997324990 +0100 >> @@ -1457,6 +1457,7 @@ >> whrhpg300n_mtdlayout=mtdparts=spi0.0:248k(u-boot)ro,8k(u-boot-env)ro,3712k(firmware),64k(art)ro >> wlr8100_mtdlayout=mtdparts=spi0.0:192k(u-boot)ro,64k(u-boot-env)ro,1408k(kernel),14080k(rootfs),192k(unknown)ro,64k(art)ro,384k(unknown2)ro,15488k@0x40000(firmware) >> wpj344_mtdlayout_16M=mtdparts=spi0.0:192k(u-boot)ro,16128k(firmware),64k(art)ro >> +dr344_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,6336k(rootfs),1408k(kernel),64k(nvram),64k(art)ro,7744k@0x50000(firmware) >> wpj531_mtdlayout_16M=mtdparts=spi0.0:192k(u-boot)ro,16128k(firmware),64k(art)ro >> wpj558_mtdlayout_16M=mtdparts=spi0.0:192k(u-boot)ro,16128k(firmware),64k(art)ro >> wndap360_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,1728k(kernel),6016k(rootfs),64k(nvram)ro,64k(art)ro,7744k@0x50000(firmware) >> @@ -2293,6 +2294,7 @@ >> $(eval $(call >> SingleProfile,AthLzma,64k,TUBE2H16M,tube2h-16M,TUBE2H,ttyATH0,115200,$$(alfa_mtdlayout_16M),KRuImage,65536)) >> $(eval $(call >> SingleProfile,AthLzma,64k,WLR8100,wlr8100,WLR8100,ttyS0,115200,$$(wlr8100_mtdlayout),KRuImage)) >> $(eval $(call >> SingleProfile,AthLzma,64k,WPJ344_16M,wpj344-16M,WPJ344,ttyS0,115200,$$(wpj344_mtdlayout_16M),KRuImage,65536)) >> +$(eval $(call >> SingleProfile,AthLzma,64k,DR344,dr344,DR344,ttyS0,115200,$$(dr344_mtdlayout),RKuImage)) >> $(eval $(call >> SingleProfile,AthLzma,64k,WPJ531_16M,wpj531-16M,WPJ531,ttyS0,115200,$$(wpj531_mtdlayout_16M),KRuImage,65536)) >> $(eval $(call >> SingleProfile,AthLzma,64k,WPJ558_16M,wpj558-16M,WPJ558,ttyS0,115200,$$(wpj558_mtdlayout_16M),KRuImage,65536)) >> >> diff -Nru >> a/target/linux/ar71xx/patches-4.1/702-MIPS-ath79-openwrt-dr344.patch >> b/target/linux/ar71xx/patches-4.1/702-MIPS-ath79-openwrt-dr344.patch >> --- >> a/target/linux/ar71xx/patches-4.1/702-MIPS-ath79-openwrt-dr344.patch1970-01-01 >> 01:00:00.000000000 +0100 >> +++ >> b/target/linux/ar71xx/patches-4.1/702-MIPS-ath79-openwrt-dr344.patch2015-10-29 >> 12:05:58.997324990 +0100 >> @@ -0,0 +1,42 @@ >> +diff -Nru a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig >> +--- a/arch/mips/ath79/Kconfig2015-10-27 22:09:32.705886861 +0100 >> ++++ b/arch/mips/ath79/Kconfig2015-10-27 22:16:08.822566162 +0100 >> +@@ -512,6 +512,16 @@ >> + select ATH79_DEV_NFC >> + select ATH79_DEV_USB >> + >> ++config ATH79_MACH_DR344 >> ++bool "Wallys DR344 board support" >> ++select SOC_AS934X >> ++select ATH79_DEV_ETH >> ++select ATH79_DEV_GPIO_BUTTONS >> ++select ATH79_DEV_LEDS_GPIO >> ++select ATH79_DEV_M25P80 >> ++select ATH79_DEV_USB >> ++select ATH79_DEV_WMAC >> ++ >> + config ATH79_MACH_DRAGINO2 >> + bool "DRAGINO V2 support" >> + select SOC_AR933X >> +diff -Nru a/arch/mips/ath79/machtypes.h b/arch/mips/ath79/machtypes.h >> +--- a/arch/mips/ath79/machtypes.h2015-10-27 22:09:32.706886873 +0100 >> ++++ b/arch/mips/ath79/machtypes.h2015-10-27 22:12:28.011957673 +0100 >> +@@ -60,6 +60,7 @@ >> + ATH79_MACH_DIR_835_A1,/* D-Link DIR-835 rev. A1 */ >> + ATH79_MACH_DLAN_PRO_500_WP,/* devolo dLAN pro 500 Wireless+ */ >> + ATH79_MACH_DLAN_PRO_1200_AC,/* devolo dLAN pro 1200+ WiFi ac*/ >> ++ATH79_MACH_DR344,/* Wallys DR344 */ >> + ATH79_MACH_DRAGINO2,/* Dragino Version 2 */ >> + ATH79_MACH_ESR900,/* EnGenius ESR900 */ >> + ATH79_MACH_EW_DORIN,/* embedded wireless Dorin Platform */ >> +diff -Nru a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile >> +--- a/arch/mips/ath79/Makefile2015-10-27 22:09:32.706886873 +0100 >> ++++ b/arch/mips/ath79/Makefile2015-10-27 22:17:18.716391867 +0100 >> +@@ -72,6 +72,7 @@ >> + obj-$(CONFIG_ATH79_MACH_DIR_615_I1)+= mach-dir-615-i1.o >> + obj-$(CONFIG_ATH79_MACH_DIR_825_B1)+= mach-dir-825-b1.o >> + obj-$(CONFIG_ATH79_MACH_DIR_825_C1)+= mach-dir-825-c1.o >> ++obj-$(CONFIG_ATH79_MACH_DR344)+= mach-dr344.o >> + obj-$(CONFIG_ATH79_MACH_DRAGINO2)+= mach-dragino2.o >> + obj-$(CONFIG_ATH79_MACH_ESR900)+= mach-esr900.o >> + obj-$(CONFIG_ATH79_MACH_EW_DORIN)+= mach-ew-dorin.o >> --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-dr344.c2015-11-07 >> 15:37:25.277919743 +0100 >> +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dr344.c2015-11-07 >> 15:37:25.277919743 +0100 >> @@ -0,0 +1,184 @@ >> +/* >> + * Wallys DR344 board support >> + * >> + * Copyright (c) 2011 Qualcomm Atheros >> + * Copyright (c) 2011-2012 Gabor Juhos >> >> >> + * Copyright (c) 2015 Philippe Duchein >> >> >> + * >> + * Permission to use, copy, modify, and/or distribute this software for any >> + * purpose with or without fee is hereby granted, provided that the above >> + * copyright notice and this permission notice appear in all copies. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES >> + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF >> + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR >> + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES >> + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN >> + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF >> + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. >> + * >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> + >> +#include >> + >> +#include "common.h" >> +#include "pci.h" >> +#include "dev-ap9x-pci.h" >> +#include "dev-gpio-buttons.h" >> +#include "dev-eth.h" >> +#include "dev-usb.h" >> +#include "dev-leds-gpio.h" >> +#include "dev-m25p80.h" >> +#include "dev-spi.h" >> +#include "dev-wmac.h" >> +#include "machtypes.h" >> + >> +#define DR344_GPIO_LED_SIG115 >> +#define DR344_GPIO_LED_SIG220 >> +#define DR344_GPIO_LED_SIG321 >> +#define DR344_GPIO_LED_SIG422 >> +#define DR344_GPIO_EXTERNAL_LNA0 18 >> +#define DR344_GPIO_EXTERNAL_LNA1 19 >> +#define DR344_GPIO_LED_STATUS14 >> + >> +#define DR344_GPIO_BTN_RESET12 >> + >> +#define DR344_KEYS_POLL_INTERVAL20/* msecs */ >> +#define DR344_KEYS_DEBOUNCE_INTERVAL(3 * DR344_KEYS_POLL_INTERVAL) >> + >> +#define DR344_MAC0_OFFSET0 >> +#define DR344_MAC1_OFFSET8 >> +#define DR344_WMAC_CALDATA_OFFSET0x1000 >> +#define DR344_PCIE_CALDATA_OFFSET0x5000 >> + >> +static struct gpio_led dr344_leds_gpio[] __initdata = { >> +{ >> +.name= "dr344:green:status", >> +.gpio= DR344_GPIO_LED_STATUS, >> +.active_low= 1, >> +}, >> +{ >> +.name= "dr344:red:sig1", >> +.gpio= DR344_GPIO_LED_SIG1, >> +.active_low= 1, >> +}, >> +{ >> +.name= "dr344:yellow:sig2", >> +.gpio= DR344_GPIO_LED_SIG2, >> +.active_low= 1, >> +}, >> +{ >> +.name= "dr344:green:sig3", >> +.gpio= DR344_GPIO_LED_SIG3, >> +.active_low= 1, >> +}, >> +{ >> +.name= "dr344:green:sig4", >> +.gpio= DR344_GPIO_LED_SIG4, >> +.active_low= 1, >> +} >> +}; >> + >> +static struct gpio_keys_button dr344_gpio_keys[] __initdata = { >> +{ >> +.desc= "reset", >> +.type= EV_KEY, >> +.code= KEY_RESTART, >> +.debounce_interval = DR344_KEYS_DEBOUNCE_INTERVAL, >> +.gpio= DR344_GPIO_BTN_RESET, >> +.active_low= 1, >> +}, >> +}; >> + >> +static struct ar8327_pad_cfg dr344_ar8327_pad0_cfg = { >> +.mode = AR8327_PAD_MAC_RGMII, >> +.txclk_delay_en = true, >> +.rxclk_delay_en = true, >> +.txclk_delay_sel = AR8327_CLK_DELAY_SEL1, >> +.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, >> +}; >> + >> +static struct ar8327_led_cfg dr344_ar8327_led_cfg = { >> +.led_ctrl0 = 0x00000000, >> +.led_ctrl1 = 0xc737c737, >> +.led_ctrl2 = 0x00000000, >> +.led_ctrl3 = 0x00c30c00, >> +.open_drain = true, >> +}; >> + >> +static struct ar8327_platform_data dr344_ar8327_data = { >> +.pad0_cfg = &dr344_ar8327_pad0_cfg, >> +.port0_cfg = { >> +.force_link = 1, >> +.speed = AR8327_PORT_SPEED_1000, >> +.duplex = 1, >> +.txpause = 1, >> +.rxpause = 1, >> +}, >> +.led_cfg = &dr344_ar8327_led_cfg, >> +}; >> + >> +static struct mdio_board_info dr344_mdio0_info[] = { >> +{ >> +.bus_id = "ag71xx-mdio.0", >> +.phy_addr = 0, >> +.platform_data = &dr344_ar8327_data, >> +}, >> +}; >> + >> +static void __init dr344_setup(void) >> +{ >> +u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); >> + >> +ath79_register_m25p80(NULL); >> +ath79_register_leds_gpio(-1, ARRAY_SIZE(dr344_leds_gpio), >> +dr344_leds_gpio); >> +ath79_register_gpio_keys_polled(-1, DR344_KEYS_POLL_INTERVAL, >> +ARRAY_SIZE(dr344_gpio_keys), >> +dr344_gpio_keys); >> + >> +ath79_register_usb(); >> + >> +ath79_wmac_set_ext_lna_gpio(0, DR344_GPIO_EXTERNAL_LNA0); >> + >> +ath79_wmac_set_ext_lna_gpio(1, DR344_GPIO_EXTERNAL_LNA1); >> + >> +ath79_register_wmac(art + DR344_WMAC_CALDATA_OFFSET, NULL); >> + >> +ath79_register_pci(); >> + >> +mdiobus_register_board_info(dr344_mdio0_info, >> +ARRAY_SIZE(dr344_mdio0_info)); >> + >> +ath79_register_mdio(1, 0x0); >> +ath79_register_mdio(0, 0x0); >> + >> +ath79_init_mac(ath79_eth0_data.mac_addr, art + DR344_MAC0_OFFSET, 0); >> + ath79_init_mac(ath79_eth1_data.mac_addr, art + >> DR344_MAC1_OFFSET, 0); >> + >> +ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | >> + AR934X_ETH_CFG_SW_ONLY_MODE); >> + >> +/* GMAC0 is connected to an AR8327 switch */ >> +ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; >> +ath79_eth0_data.phy_mask = BIT(0); >> +ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; >> +ath79_eth0_pll_data.pll_1000 = 0x0e000000; >> +ath79_eth0_pll_data.pll_100 = 0x0101; >> +ath79_eth0_pll_data.pll_10 = 0x1313; >> + >> +/* GMAC1 is connected to the internal switch */ >> +ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; >> +ath79_eth1_data.speed = SPEED_1000; >> +ath79_eth1_data.duplex = DUPLEX_FULL; >> + >> +ath79_register_eth(0); >> +ath79_register_eth(1); >> +} >> + >> +MIPS_MACHINE(ATH79_MACH_DR344, "DR344", "Wallys DR344", dr344_setup); >> >> >> >> >> >> >> >>> Le 21 nov. 2015 à 18:57, John Crispin >>> >> a écrit : >>> >>> Hi, >>> >>> 1 comment inline >>> >>> On 08/11/2015 10:46, Philippe DUCHEIN wrote: >>>> This patch is for Wallys DR344 support under OpenWRT >>>> >>>> Signed-off-by: Philippe DUCHEIN >>>> >> >>>> >>>> — >>>> >>>> diff -Nru a/target/linux/ar71xx/base-files/etc/diag.sh >>>> b/target/linux/ar71xx/base-files/etc/diag.sh >>>> --- a/target/linux/ar71xx/base-files/etc/diag.sh2015-10-27 >>>> 18:57:41.368735097 +0100 >>>> +++ b/target/linux/ar71xx/base-files/etc/diag.sh2015-10-29 >>>> 12:05:58.995324966 +0100 >>>> @@ -92,6 +92,9 @@ >>>> dlan-pro-1200-ac) >>>> status_led="devolo:status:wlan" >>>> ;; >>>> +dr344) >>>> +status_led="dr344:green:status" >>>> +;; >>>> dragino2) >>>> status_led="dragino2:red:system" >>>> ;; >>>> diff -Nru >>>> a/target/linux/ar71xx/base-files/etc/uci-defaults/02_network >>>> b/target/linux/ar71xx/base-files/etc/uci-defaults/02_network >>>> --- >>>> a/target/linux/ar71xx/base-files/etc/uci-defaults/02_network2015-10-27 18:57:41.363735040 >>>> +0100 >>>> +++ >>>> b/target/linux/ar71xx/base-files/etc/uci-defaults/02_network2015-10-29 12:05:58.995324966 >>>> +0100 >>>> @@ -17,6 +17,7 @@ >>>> case "$board" in >>>> all0315n |\ >>>> all0258n |\ >>>> +dr344 |\ >>>> ja76pf2|\ >>>> rocket-m-ti |\ >>>> ubnt-unifi-outdoor) >>>> diff -Nru a/target/linux/ar71xx/base-files/lib/ar71xx.sh >>>> b/target/linux/ar71xx/base-files/lib/ar71xx.sh >>>> --- a/target/linux/ar71xx/base-files/lib/ar71xx.sh2015-10-27 >>>> 18:57:41.341734786 +0100 >>>> +++ b/target/linux/ar71xx/base-files/lib/ar71xx.sh2015-10-29 >>>> 12:05:58.996324978 +0100 >>>> @@ -456,6 +456,9 @@ >>>> *"dLAN pro 1200+ WiFi ac") >>>> name="dlan-pro-1200-ac" >>>> ;; >>>> +*DR344) >>>> +name="dr344" >>>> +;; >>>> *"Dragino v2") >>>> name="dragino2" >>>> ;; >>>> diff -Nru a/target/linux/ar71xx/base-files/lib/upgrade/platform.sh >>>> b/target/linux/ar71xx/base-files/lib/upgrade/platform.sh >>>> --- >>>> a/target/linux/ar71xx/base-files/lib/upgrade/platform.sh2015-10-27 >>>> 18:57:41.329734649 +0100 >>>> +++ >>>> b/target/linux/ar71xx/base-files/lib/upgrade/platform.sh2015-10-29 >>>> 12:06:23.597611781 +0100 >>>> @@ -183,6 +183,7 @@ >>>> ap96 | \ >>>> bxu2000n-2-a1 | \ >>>> db120 | \ >>>> +dr344 | \ >>>> f9k1115v2 |\ >>>> hornet-ub | \ >>>> mr12 | \ >>>> diff -Nru a/target/linux/ar71xx/config-4.1 >>>> b/target/linux/ar71xx/config-4.1 >>>> --- a/target/linux/ar71xx/config-4.12015-10-27 18:57:41.379735223 +0100 >>>> +++ b/target/linux/ar71xx/config-4.12015-10-29 12:05:58.996324978 +0100 >>>> @@ -64,6 +64,7 @@ >>>> CONFIG_ATH79_MACH_DIR_825_C1=y >>>> CONFIG_ATH79_MACH_DLAN_PRO_1200_AC=y >>>> CONFIG_ATH79_MACH_DLAN_PRO_500_WP=y >>>> +CONFIG_ATH79_MACH_DR344=y >>>> CONFIG_ATH79_MACH_DRAGINO2=y >>>> CONFIG_ATH79_MACH_EAP300V2=y >>>> CONFIG_ATH79_MACH_EAP7660D=y >>>> diff -Nru a/target/linux/ar71xx/generic/profiles/wallys.mk >>>> b/target/linux/ar71xx/generic/profiles/wallys.mk >>>> --- a/target/linux/ar71xx/generic/profiles/wallys.mk1970-01-01 >>>> 01:00:00.000000000 +0100 >>>> +++ b/target/linux/ar71xx/generic/profiles/wallys.mk2015-10-29 >>>> 12:05:58.996324978 +0100 >>>> @@ -0,0 +1,17 @@ >>>> +# >>>> +# Copyright (C) 2015 Philippe DUCHEIN >>>> >> >>>> +# Copyright (C) 2009 OpenWrt.org > >>>> +# This is free software, licensed under the GNU General Public >>>> License v2. >>>> +# See /LICENSE for more information. >>>> +# >>>> + >>>> +define Profile/DR344 >>>> +NAME:=Wallys DR344 >>>> +endef >>>> + >>>> +define Profile/DR344/Description >>>> +Package set optimized for the Wallys DR344 board. >>>> +endef >>>> + >>>> +$(eval $(call Profile,DR344)) >>>> + >>>> diff -Nru a/target/linux/ar71xx/image/Makefile >>>> b/target/linux/ar71xx/image/Makefile >>>> --- a/target/linux/ar71xx/image/Makefile2015-10-27 18:57:41.248733718 >>>> +0100 >>>> +++ b/target/linux/ar71xx/image/Makefile2015-10-29 12:05:58.997324990 >>>> +0100 >>>> @@ -1457,6 +1457,7 @@ >>>> whrhpg300n_mtdlayout=mtdparts=spi0.0:248k(u-boot)ro,8k(u-boot-env)ro,3712k(firmware),64k(art)ro >>>> wlr8100_mtdlayout=mtdparts=spi0.0:192k(u-boot)ro,64k(u-boot-env)ro,1408k(kernel),14080k(rootfs),192k(unknown)ro,64k(art)ro,384k(unknown2)ro,15488k@0x40000(firmware) >>>> wpj344_mtdlayout_16M=mtdparts=spi0.0:192k(u-boot)ro,16128k(firmware),64k(art)ro >>>> +dr344_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,6336k(rootfs),1408k(kernel),64k(nvram),64k(art)ro,7744k@0x50000(firmware) >>>> wpj531_mtdlayout_16M=mtdparts=spi0.0:192k(u-boot)ro,16128k(firmware),64k(art)ro >>>> wpj558_mtdlayout_16M=mtdparts=spi0.0:192k(u-boot)ro,16128k(firmware),64k(art)ro >>>> wndap360_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,1728k(kernel),6016k(rootfs),64k(nvram)ro,64k(art)ro,7744k@0x50000(firmware) >>>> @@ -2293,6 +2294,7 @@ >>>> $(eval $(call >>>> SingleProfile,AthLzma,64k,TUBE2H16M,tube2h-16M,TUBE2H,ttyATH0,115200,$$(alfa_mtdlayout_16M),KRuImage,65536)) >>>> $(eval $(call >>>> SingleProfile,AthLzma,64k,WLR8100,wlr8100,WLR8100,ttyS0,115200,$$(wlr8100_mtdlayout),KRuImage)) >>>> $(eval $(call >>>> SingleProfile,AthLzma,64k,WPJ344_16M,wpj344-16M,WPJ344,ttyS0,115200,$$(wpj344_mtdlayout_16M),KRuImage,65536)) >>>> +$(eval $(call >>>> SingleProfile,AthLzma,64k,DR344,dr344,DR344,ttyS0,115200,$$(dr344_mtdlayout),RKuImage)) >>>> $(eval $(call >>>> SingleProfile,AthLzma,64k,WPJ531_16M,wpj531-16M,WPJ531,ttyS0,115200,$$(wpj531_mtdlayout_16M),KRuImage,65536)) >>>> $(eval $(call >>>> SingleProfile,AthLzma,64k,WPJ558_16M,wpj558-16M,WPJ558,ttyS0,115200,$$(wpj558_mtdlayout_16M),KRuImage,65536)) >>>> >>>> @@ -2424,6 +2426,7 @@ >>>> $(eval $(call MultiProfile,WP543,WP543_2M WP543_4M WP543_8M WP543_16M)) >>>> $(eval $(call MultiProfile,WPE72,WPE72_4M WPE72_8M WPE72_16M)) >>>> $(eval $(call MultiProfile,WPJ344,WPJ344_16M)) >>>> + >>> >>> you are adding a random blank line here >>> >>> John >>> >>>> $(eval $(call MultiProfile,WPJ531,WPJ531_16M)) >>>> $(eval $(call MultiProfile,WPJ558,WPJ558_16M)) >>>> >>>> diff -Nru >>>> a/target/linux/ar71xx/patches-4.1/702-MIPS-ath79-openwrt-dr344.patch >>>> b/target/linux/ar71xx/patches-4.1/702-MIPS-ath79-openwrt-dr344.patch >>>> --- >>>> a/target/linux/ar71xx/patches-4.1/702-MIPS-ath79-openwrt-dr344.patch1970-01-01 >>>> 01:00:00.000000000 +0100 >>>> +++ >>>> b/target/linux/ar71xx/patches-4.1/702-MIPS-ath79-openwrt-dr344.patch2015-10-29 >>>> 12:05:58.997324990 +0100 >>>> @@ -0,0 +1,42 @@ >>>> +diff -Nru a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig >>>> +--- a/arch/mips/ath79/Kconfig2015-10-27 22:09:32.705886861 +0100 >>>> ++++ b/arch/mips/ath79/Kconfig2015-10-27 22:16:08.822566162 +0100 >>>> +@@ -512,6 +512,16 @@ >>>> + select ATH79_DEV_NFC >>>> + select ATH79_DEV_USB >>>> + >>>> ++config ATH79_MACH_DR344 >>>> ++bool "Wallys DR344 board support" >>>> ++select SOC_AS934X >>>> ++select ATH79_DEV_ETH >>>> ++select ATH79_DEV_GPIO_BUTTONS >>>> ++select ATH79_DEV_LEDS_GPIO >>>> ++select ATH79_DEV_M25P80 >>>> ++select ATH79_DEV_USB >>>> ++select ATH79_DEV_WMAC >>>> ++ >>>> + config ATH79_MACH_DRAGINO2 >>>> + bool "DRAGINO V2 support" >>>> + select SOC_AR933X >>>> +diff -Nru a/arch/mips/ath79/machtypes.h b/arch/mips/ath79/machtypes.h >>>> +--- a/arch/mips/ath79/machtypes.h2015-10-27 22:09:32.706886873 +0100 >>>> ++++ b/arch/mips/ath79/machtypes.h2015-10-27 22:12:28.011957673 +0100 >>>> +@@ -60,6 +60,7 @@ >>>> + ATH79_MACH_DIR_835_A1,/* D-Link DIR-835 rev. A1 */ >>>> + ATH79_MACH_DLAN_PRO_500_WP,/* devolo dLAN pro 500 Wireless+ */ >>>> + ATH79_MACH_DLAN_PRO_1200_AC,/* devolo dLAN pro 1200+ WiFi ac*/ >>>> ++ATH79_MACH_DR344,/* Wallys DR344 */ >>>> + ATH79_MACH_DRAGINO2,/* Dragino Version 2 */ >>>> + ATH79_MACH_ESR900,/* EnGenius ESR900 */ >>>> + ATH79_MACH_EW_DORIN,/* embedded wireless Dorin Platform */ >>>> +diff -Nru a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile >>>> +--- a/arch/mips/ath79/Makefile2015-10-27 22:09:32.706886873 +0100 >>>> ++++ b/arch/mips/ath79/Makefile2015-10-27 22:17:18.716391867 +0100 >>>> +@@ -72,6 +72,7 @@ >>>> + obj-$(CONFIG_ATH79_MACH_DIR_615_I1)+= mach-dir-615-i1.o >>>> + obj-$(CONFIG_ATH79_MACH_DIR_825_B1)+= mach-dir-825-b1.o >>>> + obj-$(CONFIG_ATH79_MACH_DIR_825_C1)+= mach-dir-825-c1.o >>>> ++obj-$(CONFIG_ATH79_MACH_DR344)+= mach-dr344.o >>>> + obj-$(CONFIG_ATH79_MACH_DRAGINO2)+= mach-dragino2.o >>>> + obj-$(CONFIG_ATH79_MACH_ESR900)+= mach-esr900.o >>>> + obj-$(CONFIG_ATH79_MACH_EW_DORIN)+= mach-ew-dorin.o >>>> --- >>>> a/target/linux/ar71xx/files/arch/mips/ath79/mach-dr344.c2015-11-07 >>>> 15:37:25.277919743 +0100 >>>> +++ >>>> b/target/linux/ar71xx/files/arch/mips/ath79/mach-dr344.c2015-11-07 >>>> 15:37:25.277919743 +0100 >>>> @@ -0,0 +1,184 @@ >>>> +/* >>>> + * Wallys DR344 board support >>>> + * >>>> + * Copyright (c) 2011 Qualcomm Atheros >>>> + * Copyright (c) 2011-2012 Gabor Juhos >>>> >> >>>> + * Copyright (c) 2015 Philippe Duchein >>>> >> >>>> + * >>>> + * Permission to use, copy, modify, and/or distribute this software >>>> for any >>>> + * purpose with or without fee is hereby granted, provided that the >>>> above >>>> + * copyright notice and this permission notice appear in all copies. >>>> + * >>>> + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL >>>> WARRANTIES >>>> + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF >>>> + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE >>>> LIABLE FOR >>>> + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY >>>> DAMAGES >>>> + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN >>>> + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING >>>> OUT OF >>>> + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. >>>> + * >>>> + */ >>>> + >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> + >>>> +#include >>>> + >>>> +#include "common.h" >>>> +#include "pci.h" >>>> +#include "dev-ap9x-pci.h" >>>> +#include "dev-gpio-buttons.h" >>>> +#include "dev-eth.h" >>>> +#include "dev-usb.h" >>>> +#include "dev-leds-gpio.h" >>>> +#include "dev-m25p80.h" >>>> +#include "dev-spi.h" >>>> +#include "dev-wmac.h" >>>> +#include "machtypes.h" >>>> + >>>> +#define DR344_GPIO_LED_SIG115 >>>> +#define DR344_GPIO_LED_SIG220 >>>> +#define DR344_GPIO_LED_SIG321 >>>> +#define DR344_GPIO_LED_SIG422 >>>> +#define DR344_GPIO_EXTERNAL_LNA0 18 >>>> +#define DR344_GPIO_EXTERNAL_LNA1 19 >>>> +#define DR344_GPIO_LED_STATUS14 >>>> + >>>> +#define DR344_GPIO_BTN_RESET12 >>>> + >>>> +#define DR344_KEYS_POLL_INTERVAL20/* msecs */ >>>> +#define DR344_KEYS_DEBOUNCE_INTERVAL(3 * DR344_KEYS_POLL_INTERVAL) >>>> + >>>> +#define DR344_MAC0_OFFSET0 >>>> +#define DR344_MAC1_OFFSET8 >>>> +#define DR344_WMAC_CALDATA_OFFSET0x1000 >>>> +#define DR344_PCIE_CALDATA_OFFSET0x5000 >>>> + >>>> +static struct gpio_led dr344_leds_gpio[] __initdata = { >>>> +{ >>>> +.name= "dr344:green:status", >>>> +.gpio= DR344_GPIO_LED_STATUS, >>>> +.active_low= 1, >>>> +}, >>>> +{ >>>> +.name= "dr344:red:sig1", >>>> +.gpio= DR344_GPIO_LED_SIG1, >>>> +.active_low= 1, >>>> +}, >>>> +{ >>>> +.name= "dr344:yellow:sig2", >>>> +.gpio= DR344_GPIO_LED_SIG2, >>>> +.active_low= 1, >>>> +}, >>>> +{ >>>> +.name= "dr344:green:sig3", >>>> +.gpio= DR344_GPIO_LED_SIG3, >>>> +.active_low= 1, >>>> +}, >>>> +{ >>>> +.name= "dr344:green:sig4", >>>> +.gpio= DR344_GPIO_LED_SIG4, >>>> +.active_low= 1, >>>> +} >>>> +}; >>>> + >>>> +static struct gpio_keys_button dr344_gpio_keys[] __initdata = { >>>> +{ >>>> +.desc= "reset", >>>> +.type= EV_KEY, >>>> +.code= KEY_RESTART, >>>> +.debounce_interval = DR344_KEYS_DEBOUNCE_INTERVAL, >>>> +.gpio= DR344_GPIO_BTN_RESET, >>>> +.active_low= 1, >>>> +}, >>>> +}; >>>> + >>>> +static struct ar8327_pad_cfg dr344_ar8327_pad0_cfg = { >>>> +.mode = AR8327_PAD_MAC_RGMII, >>>> +.txclk_delay_en = true, >>>> +.rxclk_delay_en = true, >>>> +.txclk_delay_sel = AR8327_CLK_DELAY_SEL1, >>>> +.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, >>>> +}; >>>> + >>>> +static struct ar8327_led_cfg dr344_ar8327_led_cfg = { >>>> +.led_ctrl0 = 0x00000000, >>>> +.led_ctrl1 = 0xc737c737, >>>> +.led_ctrl2 = 0x00000000, >>>> +.led_ctrl3 = 0x00c30c00, >>>> +.open_drain = true, >>>> +}; >>>> + >>>> +static struct ar8327_platform_data dr344_ar8327_data = { >>>> +.pad0_cfg = &dr344_ar8327_pad0_cfg, >>>> +.port0_cfg = { >>>> +.force_link = 1, >>>> +.speed = AR8327_PORT_SPEED_1000, >>>> +.duplex = 1, >>>> +.txpause = 1, >>>> +.rxpause = 1, >>>> +}, >>>> +.led_cfg = &dr344_ar8327_led_cfg, >>>> +}; >>>> + >>>> +static struct mdio_board_info dr344_mdio0_info[] = { >>>> +{ >>>> +.bus_id = "ag71xx-mdio.0", >>>> +.phy_addr = 0, >>>> +.platform_data = &dr344_ar8327_data, >>>> +}, >>>> +}; >>>> + >>>> +static void __init dr344_setup(void) >>>> +{ >>>> +u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); >>>> + >>>> +ath79_register_m25p80(NULL); >>>> +ath79_register_leds_gpio(-1, ARRAY_SIZE(dr344_leds_gpio), >>>> + dr344_leds_gpio); >>>> +ath79_register_gpio_keys_polled(-1, DR344_KEYS_POLL_INTERVAL, >>>> +ARRAY_SIZE(dr344_gpio_keys), >>>> +dr344_gpio_keys); >>>> + >>>> +ath79_register_usb(); >>>> + >>>> +ath79_wmac_set_ext_lna_gpio(0, DR344_GPIO_EXTERNAL_LNA0); >>>> + >>>> +ath79_wmac_set_ext_lna_gpio(1, DR344_GPIO_EXTERNAL_LNA1); >>>> + >>>> +ath79_register_wmac(art + DR344_WMAC_CALDATA_OFFSET, NULL); >>>> + >>>> +ath79_register_pci(); >>>> + >>>> +mdiobus_register_board_info(dr344_mdio0_info, >>>> +ARRAY_SIZE(dr344_mdio0_info)); >>>> + >>>> +ath79_register_mdio(1, 0x0); >>>> +ath79_register_mdio(0, 0x0); >>>> + >>>> +ath79_init_mac(ath79_eth0_data.mac_addr, art + DR344_MAC0_OFFSET, 0); >>>> + ath79_init_mac(ath79_eth1_data.mac_addr, art + >>>> DR344_MAC1_OFFSET, 0); >>>> + >>>> +ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | >>>> + AR934X_ETH_CFG_SW_ONLY_MODE); >>>> + >>>> +/* GMAC0 is connected to an AR8327 switch */ >>>> +ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; >>>> +ath79_eth0_data.phy_mask = BIT(0); >>>> +ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; >>>> +ath79_eth0_pll_data.pll_1000 = 0x0e000000; >>>> +ath79_eth0_pll_data.pll_100 = 0x0101; >>>> +ath79_eth0_pll_data.pll_10 = 0x1313; >>>> + >>>> +/* GMAC1 is connected to the internal switch */ >>>> +ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; >>>> +ath79_eth1_data.speed = SPEED_1000; >>>> +ath79_eth1_data.duplex = DUPLEX_FULL; >>>> + >>>> +ath79_register_eth(0); >>>> +ath79_register_eth(1); >>>> +} >>>> + >>>> +MIPS_MACHINE(ATH79_MACH_DR344, "DR344", "Wallys DR344", dr344_setup); >>>> _______________________________________________ >>>> openwrt-devel mailing list >>>> openwrt-devel@lists.openwrt.org > >>>> https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel diff -Nru a/target/linux/ar71xx/base-files/etc/diag.sh b/target/linux/ar71xx/base-files/etc/diag.sh --- a/target/linux/ar71xx/base-files/etc/diag.sh 2015-10-27 18:57:41.368735097 +0100 +++ b/target/linux/ar71xx/base-files/etc/diag.sh 2015-10-29 12:05:58.995324966 +0100 @@ -92,6 +92,9 @@ dlan-pro-1200-ac) status_led="devolo:status:wlan" ;; + dr344) + status_led="dr344:green:status" + ;; dragino2) status_led="dragino2:red:system" ;; diff -Nru a/target/linux/ar71xx/base-files/etc/board.d/02_network b/target/linux/ar71xx/base-files/etc/board.d/02_network --- a/target/linux/ar71xx/base-files/etc/board.d/02_network 2015-10-27 18:57:41.363735040 +0100 +++ b/target/linux/ar71xx/base-files/etc/board.d/02_network 2015-10-29 12:05:58.995324966 +0100 @@ -17,6 +17,7 @@ case "$board" in all0315n |\ all0258n |\ +dr344 |\ ja76pf2|\ rocket-m-ti |\ ubnt-unifi-outdoor) diff -Nru a/target/linux/ar71xx/base-files/lib/ar71xx.sh b/target/linux/ar71xx/base-files/lib/ar71xx.sh --- a/target/linux/ar71xx/base-files/lib/ar71xx.sh 2015-10-27 18:57:41.341734786 +0100 +++ b/target/linux/ar71xx/base-files/lib/ar71xx.sh 2015-10-29 12:05:58.996324978 +0100 @@ -456,6 +456,9 @@ *"dLAN pro 1200+ WiFi ac") name="dlan-pro-1200-ac" ;; + *DR344) + name="dr344" + ;; *"Dragino v2") name="dragino2" ;; diff -Nru a/target/linux/ar71xx/base-files/lib/upgrade/platform.sh b/target/linux/ar71xx/base-files/lib/upgrade/platform.sh --- a/target/linux/ar71xx/base-files/lib/upgrade/platform.sh 2015-10-27 18:57:41.329734649 +0100 +++ b/target/linux/ar71xx/base-files/lib/upgrade/platform.sh 2015-10-29 12:06:23.597611781 +0100 @@ -183,6 +183,7 @@ ap96 | \ bxu2000n-2-a1 | \ db120 | \ + dr344 | \ f9k1115v2 |\ hornet-ub | \ mr12 | \ diff -Nru a/target/linux/ar71xx/config-4.1 b/target/linux/ar71xx/config-4.1 --- a/target/linux/ar71xx/config-4.1 2015-10-27 18:57:41.379735223 +0100 +++ b/target/linux/ar71xx/config-4.1 2015-10-29 12:05:58.996324978 +0100 @@ -64,6 +64,7 @@ CONFIG_ATH79_MACH_DLAN_HOTSPOT=y CONFIG_ATH79_MACH_DLAN_PRO_1200_AC=y CONFIG_ATH79_MACH_DLAN_PRO_500_WP=y +CONFIG_ATH79_MACH_DR344=y CONFIG_ATH79_MACH_GL_DOMINO=y CONFIG_ATH79_MACH_DRAGINO2=y CONFIG_ATH79_MACH_EAP300V2=y diff -Nru a/target/linux/ar71xx/generic/profiles/wallys.mk b/target/linux/ar71xx/generic/profiles/wallys.mk --- a/target/linux/ar71xx/generic/profiles/wallys.mk 1970-01-01 01:00:00.000000000 +0100 +++ b/target/linux/ar71xx/generic/profiles/wallys.mk 2015-10-29 12:05:58.996324978 +0100 @@ -0,0 +1,17 @@ +# +# Copyright (C) 2015 Philippe DUCHEIN +# Copyright (C) 2009 OpenWrt.org +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/DR344 + NAME:=Wallys DR344 +endef + +define Profile/DR344/Description + Package set optimized for the Wallys DR344 board. +endef + +$(eval $(call Profile,DR344)) + diff -Nru a/target/linux/ar71xx/image/Makefile b/target/linux/ar71xx/image/Makefile --- a/target/linux/ar71xx/image/Makefile 2015-10-27 18:57:41.248733718 +0100 +++ b/target/linux/ar71xx/image/Makefile 2015-10-29 12:05:58.997324990 +0100 @@ -1457,6 +1457,7 @@ whrhpg300n_mtdlayout=mtdparts=spi0.0:248k(u-boot)ro,8k(u-boot-env)ro,3712k(firmware),64k(art)ro wlr8100_mtdlayout=mtdparts=spi0.0:192k(u-boot)ro,64k(u-boot-env)ro,1408k(kernel),14080k(rootfs),192k(unknown)ro,64k(art)ro,384k(unknown2)ro,15488k@0x40000(firmware) wpj344_mtdlayout_16M=mtdparts=spi0.0:192k(u-boot)ro,16128k(firmware),64k(art)ro +dr344_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,6336k(rootfs),1408k(kernel),64k(nvram),64k(art)ro,7744k@0x50000(firmware) wpj531_mtdlayout_16M=mtdparts=spi0.0:192k(u-boot)ro,16128k(firmware),64k(art)ro wpj558_mtdlayout_16M=mtdparts=spi0.0:192k(u-boot)ro,16128k(firmware),64k(art)ro wndap360_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,1728k(kernel),6016k(rootfs),64k(nvram)ro,64k(art)ro,7744k@0x50000(firmware) @@ -2293,6 +2294,7 @@ $(eval $(call SingleProfile,AthLzma,64k,TUBE2H16M,tube2h-16M,TUBE2H,ttyATH0,115200,$$(alfa_mtdlayout_16M),KRuImage,65536)) $(eval $(call SingleProfile,AthLzma,64k,WLR8100,wlr8100,WLR8100,ttyS0,115200,$$(wlr8100_mtdlayout),KRuImage)) $(eval $(call SingleProfile,AthLzma,64k,WPJ344_16M,wpj344-16M,WPJ344,ttyS0,115200,$$(wpj344_mtdlayout_16M),KRuImage,65536)) +$(eval $(call SingleProfile,AthLzma,64k,DR344,dr344,DR344,ttyS0,115200,$$(dr344_mtdlayout),RKuImage)) $(eval $(call SingleProfile,AthLzma,64k,WPJ531_16M,wpj531-16M,WPJ531,ttyS0,115200,$$(wpj531_mtdlayout_16M),KRuImage,65536)) $(eval $(call SingleProfile,AthLzma,64k,WPJ558_16M,wpj558-16M,WPJ558,ttyS0,115200,$$(wpj558_mtdlayout_16M),KRuImage,65536)) diff -Nru a/target/linux/ar71xx/patches-4.1/702-MIPS-ath79-openwrt-dr344.patch b/target/linux/ar71xx/patches-4.1/702-MIPS-ath79-openwrt-dr344.patch --- a/target/linux/ar71xx/patches-4.1/702-MIPS-ath79-openwrt-dr344.patch 1970-01-01 01:00:00.000000000 +0100 +++ b/target/linux/ar71xx/patches-4.1/702-MIPS-ath79-openwrt-dr344.patch 2015-10-29 12:05:58.997324990 +0100 @@ -0,0 +1,42 @@ +diff -Nru a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig +--- a/arch/mips/ath79/Kconfig 2015-10-27 22:09:32.705886861 +0100 ++++ b/arch/mips/ath79/Kconfig 2015-10-27 22:16:08.822566162 +0100 +@@ -512,6 +512,16 @@ + select ATH79_DEV_NFC + select ATH79_DEV_USB + ++config ATH79_MACH_DR344 ++ bool "Wallys DR344 board support" ++ select SOC_AS934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ + config ATH79_MACH_DRAGINO2 + bool "DRAGINO V2 support" + select SOC_AR933X +diff -Nru a/arch/mips/ath79/machtypes.h b/arch/mips/ath79/machtypes.h +--- a/arch/mips/ath79/machtypes.h 2015-10-27 22:09:32.706886873 +0100 ++++ b/arch/mips/ath79/machtypes.h 2015-10-27 22:12:28.011957673 +0100 +@@ -60,6 +60,7 @@ + ATH79_MACH_DIR_835_A1, /* D-Link DIR-835 rev. A1 */ + ATH79_MACH_DLAN_PRO_500_WP, /* devolo dLAN pro 500 Wireless+ */ + ATH79_MACH_DLAN_PRO_1200_AC, /* devolo dLAN pro 1200+ WiFi ac*/ ++ ATH79_MACH_DR344, /* Wallys DR344 */ + ATH79_MACH_DRAGINO2, /* Dragino Version 2 */ + ATH79_MACH_ESR900, /* EnGenius ESR900 */ + ATH79_MACH_EW_DORIN, /* embedded wireless Dorin Platform */ +diff -Nru a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile +--- a/arch/mips/ath79/Makefile 2015-10-27 22:09:32.706886873 +0100 ++++ b/arch/mips/ath79/Makefile 2015-10-27 22:17:18.716391867 +0100 +@@ -72,6 +72,7 @@ + obj-$(CONFIG_ATH79_MACH_DIR_615_I1) += mach-dir-615-i1.o + obj-$(CONFIG_ATH79_MACH_DIR_825_B1) += mach-dir-825-b1.o + obj-$(CONFIG_ATH79_MACH_DIR_825_C1) += mach-dir-825-c1.o ++obj-$(CONFIG_ATH79_MACH_DR344) += mach-dr344.o + obj-$(CONFIG_ATH79_MACH_DRAGINO2) += mach-dragino2.o + obj-$(CONFIG_ATH79_MACH_ESR900) += mach-esr900.o + obj-$(CONFIG_ATH79_MACH_EW_DORIN) += mach-ew-dorin.o --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-dr344.c 2015-11-07 15:37:25.277919743 +0100 +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dr344.c 2015-11-07 15:37:25.277919743 +0100 @@ -0,0 +1,184 @@ +/* + * Wallys DR344 board support + * + * Copyright (c) 2011 Qualcomm Atheros + * Copyright (c) 2011-2012 Gabor Juhos + * Copyright (c) 2015 Philippe Duchein + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include +#include + +#include + +#include "common.h" +#include "pci.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-usb.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define DR344_GPIO_LED_SIG1 15 +#define DR344_GPIO_LED_SIG2 20 +#define DR344_GPIO_LED_SIG3 21 +#define DR344_GPIO_LED_SIG4 22 +#define DR344_GPIO_EXTERNAL_LNA0 18 +#define DR344_GPIO_EXTERNAL_LNA1 19 +#define DR344_GPIO_LED_STATUS 14 + +#define DR344_GPIO_BTN_RESET 12 + +#define DR344_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DR344_KEYS_DEBOUNCE_INTERVAL (3 * DR344_KEYS_POLL_INTERVAL) + +#define DR344_MAC0_OFFSET 0 +#define DR344_MAC1_OFFSET 8 +#define DR344_WMAC_CALDATA_OFFSET 0x1000 +#define DR344_PCIE_CALDATA_OFFSET 0x5000 + +static struct gpio_led dr344_leds_gpio[] __initdata = { + { + .name = "dr344:green:status", + .gpio = DR344_GPIO_LED_STATUS, + .active_low = 1, + }, + { + .name = "dr344:red:sig1", + .gpio = DR344_GPIO_LED_SIG1, + .active_low = 1, + }, + { + .name = "dr344:yellow:sig2", + .gpio = DR344_GPIO_LED_SIG2, + .active_low = 1, + }, + { + .name = "dr344:green:sig3", + .gpio = DR344_GPIO_LED_SIG3, + .active_low = 1, + }, + { + .name = "dr344:green:sig4", + .gpio = DR344_GPIO_LED_SIG4, + .active_low = 1, + } +}; + +static struct gpio_keys_button dr344_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DR344_KEYS_DEBOUNCE_INTERVAL, + .gpio = DR344_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg dr344_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_led_cfg dr344_ar8327_led_cfg = { + .led_ctrl0 = 0x00000000, + .led_ctrl1 = 0xc737c737, + .led_ctrl2 = 0x00000000, + .led_ctrl3 = 0x00c30c00, + .open_drain = true, +}; + +static struct ar8327_platform_data dr344_ar8327_data = { + .pad0_cfg = &dr344_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .led_cfg = &dr344_ar8327_led_cfg, +}; + +static struct mdio_board_info dr344_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &dr344_ar8327_data, + }, +}; + +static void __init dr344_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + ath79_register_leds_gpio(-1, ARRAY_SIZE(dr344_leds_gpio), + dr344_leds_gpio); + ath79_register_gpio_keys_polled(-1, DR344_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dr344_gpio_keys), + dr344_gpio_keys); + + ath79_register_usb(); + + ath79_wmac_set_ext_lna_gpio(0, DR344_GPIO_EXTERNAL_LNA0); + + ath79_wmac_set_ext_lna_gpio(1, DR344_GPIO_EXTERNAL_LNA1); + + ath79_register_wmac(art + DR344_WMAC_CALDATA_OFFSET, NULL); + + ath79_register_pci(); + + mdiobus_register_board_info(dr344_mdio0_info, + ARRAY_SIZE(dr344_mdio0_info)); + + ath79_register_mdio(1, 0x0); + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, art + DR344_MAC0_OFFSET, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, art + DR344_MAC1_OFFSET, 0); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | + AR934X_ETH_CFG_SW_ONLY_MODE); + + /* GMAC0 is connected to an AR8327 switch */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x0e000000; + ath79_eth0_pll_data.pll_100 = 0x0101; + ath79_eth0_pll_data.pll_10 = 0x1313; + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + ath79_register_eth(1); +} + +MIPS_MACHINE(ATH79_MACH_DR344, "DR344", "Wallys DR344", dr344_setup);