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[OpenWrt-Devel] AR8334 switch support

Message ID 553FE953.6090707@gmail.com
State Not Applicable
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Commit Message

Heiner Kallweit April 28, 2015, 8:10 p.m. UTC 
Am 28.04.2015 um 20:37 schrieb Heiner Kallweit:
> Am 28.04.2015 um 14:15 schrieb Christian Mehlis:
>> Am 27.04.2015 um 20:56 schrieb Heiner Kallweit:
>>> The only other difference I found is the initial setting of LED_CTRL3 register.
>>> Could you please test the following patch (first remove the initial patch attempt)?
>>
>> [    0.850000] switch0: Atheros AR833X rev. 2 switch registered on ag71xx-mdio.0
>> [    0.860000] Atheros AR8216/AR8236/AR8316 ag71xx-mdio.0:00: led_val = 3f
>> [    0.860000] Atheros AR8216/AR8236/AR8316 ag71xx-mdio.0:00: Detected AR8337
>>
>> It seems that we have no luck here...
>> In case you have any new idea I'll test the patch.
>>
>> Here is a picture of the switch chip:
>> http://c33.imgup.net/2015-04-166a5b.jpg
>>
>> Best
>> Christian
>> .
>>
> I found a datasheet for QCA8334 and according to it these bits in LED_CTRl3 are supposed to
> be 0 for this chip. But this doesn't seem to be true ..
> Meanwhile I'm running out of ideas how to tell between the two chips.
> 
> However I have another hypothesis:
> The drivers sets bit MAC06_EXCHANGE_EN for AR8337. According to the datasheet this means
> "Exchange MAC0 and MAC6". My assumption is that MAC6 is used as CPU port if this bit is set.
> Having said this whether to set this bit or not might not be chip-specific but board-specific
> (CPU connected to MAC0 vs. MAC6 pins of the switch chip).
> AR8334 has no MAC6 (R)GMII pins therefore this bit must not be set.
> Not sure how many supported devices actually use an AR8337. Maybe they share some
> reference design and use MAC6 in general?
> Conclusion would be that the driver can not know whether to set the bit or not. It would
> have to be defined in platform configuration or device tree.
> 
> I'm not an expert and refactored few parts of the driver only.
> Therefore I can not promise any quick results, however I'll have a look at it.
> 
> Rgds, Heiner
> 

It was easier than I thought, here comes the related patch.

Known limitations:
1. The patch supports configuration of this bit for platform-data-configured
   platforms only. DT-based platforms would need a similar extension.
2. For now it's for WPJ344 only. Every other AR8334-based device would need the same
   extension to the platform data.

Rgds, Heiner

---
 target/linux/ar71xx/files/arch/mips/ath79/mach-wpj344.c    | 1 +
 target/linux/generic/files/drivers/net/phy/ar8327.c        | 5 ++++-
 target/linux/generic/files/include/linux/ar8216_platform.h | 4 +++-
 3 files changed, 8 insertions(+), 2 deletions(-)

Comments

Christian Mehlis April 29, 2015, 9:26 a.m. UTC | #1 
Am 28.04.2015 um 22:10 schrieb Heiner Kallweit:
> It was easier than I thought, here comes the related patch.
>
> Known limitations:
> 1. The patch supports configuration of this bit for platform-data-configured
>     platforms only. DT-based platforms would need a similar extension.
> 2. For now it's for WPJ344 only. Every other AR8334-based device would need the same
>     extension to the platform data.
>
> Rgds, Heiner

Hi Heiner,

this explicit way to talk to the driver is working!
Thank you for your effort!

Tested-By: Christian Mehlis <christian@m3hlis.de>

##########################################################

Perhaps you know the answer to my last problem with this hardware too:

On plug/unplug I get those events:

[   25.120000] Atheros AR8216/AR8236/AR8316 ag71xx-mdio.0:00: Port 2 is up
[   37.130000] Atheros AR8216/AR8236/AR8316 ag71xx-mdio.0:00: Port 2 is down

but the linux network stack is keeping the interface UP.

config interface 'wan'
         option ifname 'eth0.2'
         option proto 'dhcp'

config switch
         option name 'switch0'
         option reset '1'
         option enable_vlan '1'

config switch_vlan
         option device 'switch0'
         option vlan '1'
         option ports '0t 3'

config switch_vlan
         option device 'switch0'
         option vlan '2'
         option ports '0t 2'

I have never had this behaviour on other platforms...do you think the 
compex-344 specific initialization is done wrong?

#########################################################

Best
Christian
Heiner Kallweit April 29, 2015, 9:41 a.m. UTC | #2 
On Wed, Apr 29, 2015 at 11:26 AM, Christian Mehlis <christian@m3hlis.de> wrote:
> On plug/unplug I get those events:
>
> [   25.120000] Atheros AR8216/AR8236/AR8316 ag71xx-mdio.0:00: Port 2 is up
> [   37.130000] Atheros AR8216/AR8236/AR8316 ag71xx-mdio.0:00: Port 2 is down
>
> but the linux network stack is keeping the interface UP.


IMHO that's no contradiction. If the port is disconnected the
interface should no longer be LOWER_UP.
UP just means it's enabled, not necessarily connected.

Rgds, Heiner
Christian Mehlis April 29, 2015, 2:16 p.m. UTC | #3 
Am 28.04.2015 um 22:10 schrieb Heiner Kallweit:
> It was easier than I thought, here comes the related patch.

do you plan to send this as a patch to make the change available for 
everyone, or should I?

Best
Christian
Heiner Kallweit April 29, 2015, 2:44 p.m. UTC | #4 
I still have to adjust it to make handling of the new platform
parameter more consistent with general handling of platform data.
Most likely I can submit the final patch by today.

Rgds, Heiner

On Wed, Apr 29, 2015 at 4:16 PM, Christian Mehlis <christian@m3hlis.de> wrote:
> Am 28.04.2015 um 22:10 schrieb Heiner Kallweit:
>>
>> It was easier than I thought, here comes the related patch.
>
>
> do you plan to send this as a patch to make the change available for
> everyone, or should I?
>
> Best
> Christian
diff mbox

Patch

diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj344.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj344.c
index fd718bd..590778e 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj344.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj344.c
@@ -98,6 +98,7 @@  static struct ar8327_pad_cfg wpj344_ar8327_pad0_cfg = {
 	.rxclk_delay_en = true,
 	.txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
 	.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
+	.mac06_exchange_en = -1,
 };
 
 static struct ar8327_led_cfg wpj344_ar8327_led_cfg = {
diff --git a/target/linux/generic/files/drivers/net/phy/ar8327.c b/target/linux/generic/files/drivers/net/phy/ar8327.c
index 07e837e..772d03f 100644
--- a/target/linux/generic/files/drivers/net/phy/ar8327.c
+++ b/target/linux/generic/files/drivers/net/phy/ar8327.c
@@ -124,6 +124,9 @@  ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
 		break;
 	}
 
+	if (cfg->mac06_exchange_en == 1)
+		t |= AR8337_PAD_MAC06_EXCHANGE_EN;
+
 	return t;
 }
 
@@ -508,7 +511,7 @@  ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
 	data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
 
 	t = ar8327_get_pad_cfg(pdata->pad0_cfg);
-	if (chip_is_ar8337(priv))
+	if (chip_is_ar8337(priv) && pdata->pad0_cfg->mac06_exchange_en == 0)
 		t |= AR8337_PAD_MAC06_EXCHANGE_EN;
 
 	ar8xxx_write(priv, AR8327_REG_PAD0_MODE, t);
diff --git a/target/linux/generic/files/include/linux/ar8216_platform.h b/target/linux/generic/files/include/linux/ar8216_platform.h
index 4935ad3..821ff27 100644
--- a/target/linux/generic/files/include/linux/ar8216_platform.h
+++ b/target/linux/generic/files/include/linux/ar8216_platform.h
@@ -47,6 +47,8 @@  struct ar8327_pad_cfg {
 	bool sgmii_delay_en;
 	enum ar8327_clk_delay_sel txclk_delay_sel;
 	enum ar8327_clk_delay_sel rxclk_delay_sel;
+	/* 0 = use driver default -1 = disable 1 = enable */
+	int mac06_exchange_en;
 };
 
 enum ar8327_port_speed {
@@ -128,4 +130,4 @@  struct ar8327_platform_data {
 	const struct ar8327_led_info *leds;
 };
 
-#endif /* AR8216_PLATFORM_H */
\ No newline at end of file
+#endif /* AR8216_PLATFORM_H */