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Sun, 04 Apr 2021 14:07:27 -0700 (PDT) From: Daniel =?iso-8859-1?q?Gonz=E1lez?= Cabanelas To: openwrt-devel@lists.openwrt.org, daniel@makrotopia.org, thomas.petazzoni@bootlin.com, hauke@hauke-m.de Subject: [PATCH] mvebu: armada 370: dts: fix the crypto engine Date: Sun, 04 Apr 2021 23:06:46 +0200 Message-ID: <405110637.nMEbgGFN7n@tool> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210404_220734_630925_643802C0 X-CRM114-Status: GOOD ( 11.55 ) X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "desiato.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: The crypto engine in Armada 370 SoCs is currently broken. It can be checked installing the required packages for testing openssl with hw acceleration: opkg install openssl-util opkg install kmod-cryptodev opkg install libopenssl-devcrypto Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:42e listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [dgcbueu[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org The crypto engine in Armada 370 SoCs is currently broken. It can be checked installing the required packages for testing openssl with hw acceleration: opkg install openssl-util opkg install kmod-cryptodev opkg install libopenssl-devcrypto After configuring /etc/ssl/openssl.cnf to let openssl use the crypto engine for digest operations, and performing some checksums.. md5sum 10M-file.bin openssl md5 10M-file.bin ...we can see they don't match. There might be an alignment or size constraint issue caused by the idle-sram area. Use the whole crypto sram and disable the idle-sram area to fix it. Also disable the idle support by adding the broken-idle property to prevent accessing the disabled idle-sram. We don't care about disabling the idle support since it is already broken in Armada 370 causing a huge performance loss because it disables permanently the L2 cache. This was reported in the Openwrt forum and elsewhere by Debian users with different board models. Signed-off-by: Daniel González Cabanelas --- ...317-armada-370-dts-fix-crypto-engine.patch | 29 +++++++++++++++++++ ...320-armada-370-dts-fix-crypto-engine.patch | 29 +++++++++++++++++++ 2 files changed, 58 insertions(+) create mode 100644 target/linux/mvebu/patches-5.10/317-armada-370-dts-fix-crypto-engine.patch create mode 100644 target/linux/mvebu/patches-5.4/320-armada-370-dts-fix-crypto-engine.patch diff --git a/target/linux/mvebu/patches-5.10/317-armada-370-dts-fix-crypto-engine.patch b/target/linux/mvebu/patches-5.10/317-armada-370-dts-fix-crypto-engine.patch new file mode 100644 index 0000000..1937887 --- /dev/null +++ b/target/linux/mvebu/patches-5.10/317-armada-370-dts-fix-crypto-engine.patch @@ -0,0 +1,29 @@ +--- a/arch/arm/boot/dts/armada-370.dtsi ++++ b/arch/arm/boot/dts/armada-370.dtsi +@@ -234,7 +234,7 @@ + clocks = <&gateclk 23>; + clock-names = "cesa0"; + marvell,crypto-srams = <&crypto_sram>; +- marvell,crypto-sram-size = <0x7e0>; ++ marvell,crypto-sram-size = <0x800>; + }; + }; + +@@ -255,12 +255,17 @@ + * cpuidle workaround. + */ + idle-sram@0 { ++ status = "disabled"; + reg = <0x0 0x20>; + }; + }; + }; + }; + ++&coherencyfab { ++ broken-idle; ++}; ++ + /* + * Default UART pinctrl setting without RTS/CTS, can be overwritten on + * board level if a different configuration is used. diff --git a/target/linux/mvebu/patches-5.4/320-armada-370-dts-fix-crypto-engine.patch b/target/linux/mvebu/patches-5.4/320-armada-370-dts-fix-crypto-engine.patch new file mode 100644 index 0000000..1937887 --- /dev/null +++ b/target/linux/mvebu/patches-5.4/320-armada-370-dts-fix-crypto-engine.patch @@ -0,0 +1,29 @@ +--- a/arch/arm/boot/dts/armada-370.dtsi ++++ b/arch/arm/boot/dts/armada-370.dtsi +@@ -234,7 +234,7 @@ + clocks = <&gateclk 23>; + clock-names = "cesa0"; + marvell,crypto-srams = <&crypto_sram>; +- marvell,crypto-sram-size = <0x7e0>; ++ marvell,crypto-sram-size = <0x800>; + }; + }; + +@@ -255,12 +255,17 @@ + * cpuidle workaround. + */ + idle-sram@0 { ++ status = "disabled"; + reg = <0x0 0x20>; + }; + }; + }; + }; + ++&coherencyfab { ++ broken-idle; ++}; ++ + /* + * Default UART pinctrl setting without RTS/CTS, can be overwritten on + * board level if a different configuration is used.