diff mbox series

mvebu: armada 370: dts: fix the crypto engine

Message ID 405110637.nMEbgGFN7n@tool
State Accepted
Delegated to: Hauke Mehrtens
Headers show
Series mvebu: armada 370: dts: fix the crypto engine | expand

Commit Message

Daniel González Cabanelas April 4, 2021, 9:06 p.m. UTC
The crypto engine in Armada 370 SoCs is currently broken. It can be
checked installing the required packages for testing openssl with hw
acceleration:

  opkg install openssl-util 
  opkg install kmod-cryptodev
  opkg install libopenssl-devcrypto 

After configuring /etc/ssl/openssl.cnf to let openssl use the crypto
engine for digest operations, and performing some checksums..

  md5sum 10M-file.bin 
  openssl md5 10M-file.bin

...we can see they don't match.

There might be an alignment or size constraint issue caused by the
idle-sram area.

Use the whole crypto sram and disable the idle-sram area to fix it. Also
disable the idle support by adding the broken-idle property to prevent
accessing the disabled idle-sram.

We don't care about disabling the idle support since it is already broken
in Armada 370 causing a huge performance loss because it disables
permanently the L2 cache. This was reported in the Openwrt forum and
elsewhere by Debian users with different board models.

Signed-off-by: Daniel González Cabanelas <dgcbueu@gmail.com>
---
 ...317-armada-370-dts-fix-crypto-engine.patch | 29 +++++++++++++++++++
 ...320-armada-370-dts-fix-crypto-engine.patch | 29 +++++++++++++++++++
 2 files changed, 58 insertions(+)
 create mode 100644 target/linux/mvebu/patches-5.10/317-armada-370-dts-fix-crypto-engine.patch
 create mode 100644 target/linux/mvebu/patches-5.4/320-armada-370-dts-fix-crypto-engine.patch

Comments

Hauke Mehrtens April 5, 2021, 12:55 p.m. UTC | #1
On 4/4/21 11:06 PM, Daniel González Cabanelas wrote:
> The crypto engine in Armada 370 SoCs is currently broken. It can be
> checked installing the required packages for testing openssl with hw
> acceleration:
> 
>    opkg install openssl-util
>    opkg install kmod-cryptodev
>    opkg install libopenssl-devcrypto
> 
> After configuring /etc/ssl/openssl.cnf to let openssl use the crypto
> engine for digest operations, and performing some checksums..
> 
>    md5sum 10M-file.bin
>    openssl md5 10M-file.bin
> 
> ...we can see they don't match.
> 
> There might be an alignment or size constraint issue caused by the
> idle-sram area.
> 
> Use the whole crypto sram and disable the idle-sram area to fix it. Also
> disable the idle support by adding the broken-idle property to prevent
> accessing the disabled idle-sram.
> 
> We don't care about disabling the idle support since it is already broken
> in Armada 370 causing a huge performance loss because it disables
> permanently the L2 cache. This was reported in the Openwrt forum and
> elsewhere by Debian users with different board models.

Is the L2 cache disabled without or with this patch?

> 
> Signed-off-by: Daniel González Cabanelas <dgcbueu@gmail.com>

Could you send this also to the upstream Linux maintainers, I would like 
to get their opinion on this and if this is correct it should also go 
into upstream Linux.

Hauke
Daniel González Cabanelas April 5, 2021, 1:18 p.m. UTC | #2
Hi Hauke,

El lun, 5 abr 2021 a las 14:55, Hauke Mehrtens (<hauke@hauke-m.de>) escribió:
>
> On 4/4/21 11:06 PM, Daniel González Cabanelas wrote:
> > The crypto engine in Armada 370 SoCs is currently broken. It can be
> > checked installing the required packages for testing openssl with hw
> > acceleration:
> >
> >    opkg install openssl-util
> >    opkg install kmod-cryptodev
> >    opkg install libopenssl-devcrypto
> >
> > After configuring /etc/ssl/openssl.cnf to let openssl use the crypto
> > engine for digest operations, and performing some checksums..
> >
> >    md5sum 10M-file.bin
> >    openssl md5 10M-file.bin
> >
> > ...we can see they don't match.
> >
> > There might be an alignment or size constraint issue caused by the
> > idle-sram area.
> >
> > Use the whole crypto sram and disable the idle-sram area to fix it. Also
> > disable the idle support by adding the broken-idle property to prevent
> > accessing the disabled idle-sram.
> >
> > We don't care about disabling the idle support since it is already broken
> > in Armada 370 causing a huge performance loss because it disables
> > permanently the L2 cache. This was reported in the Openwrt forum and
> > elsewhere by Debian users with different board models.
>
> Is the L2 cache disabled without or with this patch?

The L2 Aurora cache is always disabled without the patch.

With this patch it is enabled, therefore it fixes the crypto engine
and also the L2 cache issue. The side effect is a disabled idle
support which can be considered broken anyway.

>
> >
> > Signed-off-by: Daniel González Cabanelas <dgcbueu@gmail.com>
>
> Could you send this also to the upstream Linux maintainers, I would like
> to get their opinion on this and if this is correct it should also go
> into upstream Linux.
>
Sure. I'll wait a bit to see if Thomas Petazzoni is aware of the
problem replying to this mail.

> Hauke

Thank you
Daniel
Christian Marangi April 5, 2021, 1:25 p.m. UTC | #3
>
> Hi Hauke,
>
> El lun, 5 abr 2021 a las 14:55, Hauke Mehrtens (<hauke@hauke-m.de>) escribió:
> >
> > On 4/4/21 11:06 PM, Daniel González Cabanelas wrote:
> > > The crypto engine in Armada 370 SoCs is currently broken. It can be
> > > checked installing the required packages for testing openssl with hw
> > > acceleration:
> > >
> > >    opkg install openssl-util
> > >    opkg install kmod-cryptodev
> > >    opkg install libopenssl-devcrypto
> > >
> > > After configuring /etc/ssl/openssl.cnf to let openssl use the crypto
> > > engine for digest operations, and performing some checksums..
> > >
> > >    md5sum 10M-file.bin
> > >    openssl md5 10M-file.bin
> > >
> > > ...we can see they don't match.
> > >
> > > There might be an alignment or size constraint issue caused by the
> > > idle-sram area.
> > >
> > > Use the whole crypto sram and disable the idle-sram area to fix it. Also
> > > disable the idle support by adding the broken-idle property to prevent
> > > accessing the disabled idle-sram.
> > >
> > > We don't care about disabling the idle support since it is already broken
> > > in Armada 370 causing a huge performance loss because it disables
> > > permanently the L2 cache. This was reported in the Openwrt forum and
> > > elsewhere by Debian users with different board models.
> >
> > Is the L2 cache disabled without or with this patch?
>
> The L2 Aurora cache is always disabled without the patch.
>
> With this patch it is enabled, therefore it fixes the crypto engine
> and also the L2 cache issue. The side effect is a disabled idle
> support which can be considered broken anyway.
>

Consider the fact that cpu-idle is disabled on mvebu by default so no
regression.
(there is a big warning about broken cpu-idle in the bootlog)
diff mbox series

Patch

diff --git a/target/linux/mvebu/patches-5.10/317-armada-370-dts-fix-crypto-engine.patch b/target/linux/mvebu/patches-5.10/317-armada-370-dts-fix-crypto-engine.patch
new file mode 100644
index 0000000..1937887
--- /dev/null
+++ b/target/linux/mvebu/patches-5.10/317-armada-370-dts-fix-crypto-engine.patch
@@ -0,0 +1,29 @@ 
+--- a/arch/arm/boot/dts/armada-370.dtsi
++++ b/arch/arm/boot/dts/armada-370.dtsi
+@@ -234,7 +234,7 @@
+ 				clocks = <&gateclk 23>;
+ 				clock-names = "cesa0";
+ 				marvell,crypto-srams = <&crypto_sram>;
+-				marvell,crypto-sram-size = <0x7e0>;
++				marvell,crypto-sram-size = <0x800>;
+ 			};
+ 		};
+ 
+@@ -255,12 +255,17 @@
+ 			 * cpuidle workaround.
+ 			 */
+ 			idle-sram@0 {
++				status = "disabled";
+ 				reg = <0x0 0x20>;
+ 			};
+ 		};
+ 	};
+ };
+ 
++&coherencyfab {
++	broken-idle;
++};
++
+ /*
+  * Default UART pinctrl setting without RTS/CTS, can be overwritten on
+  * board level if a different configuration is used.
diff --git a/target/linux/mvebu/patches-5.4/320-armada-370-dts-fix-crypto-engine.patch b/target/linux/mvebu/patches-5.4/320-armada-370-dts-fix-crypto-engine.patch
new file mode 100644
index 0000000..1937887
--- /dev/null
+++ b/target/linux/mvebu/patches-5.4/320-armada-370-dts-fix-crypto-engine.patch
@@ -0,0 +1,29 @@ 
+--- a/arch/arm/boot/dts/armada-370.dtsi
++++ b/arch/arm/boot/dts/armada-370.dtsi
+@@ -234,7 +234,7 @@
+ 				clocks = <&gateclk 23>;
+ 				clock-names = "cesa0";
+ 				marvell,crypto-srams = <&crypto_sram>;
+-				marvell,crypto-sram-size = <0x7e0>;
++				marvell,crypto-sram-size = <0x800>;
+ 			};
+ 		};
+ 
+@@ -255,12 +255,17 @@
+ 			 * cpuidle workaround.
+ 			 */
+ 			idle-sram@0 {
++				status = "disabled";
+ 				reg = <0x0 0x20>;
+ 			};
+ 		};
+ 	};
+ };
+ 
++&coherencyfab {
++	broken-idle;
++};
++
+ /*
+  * Default UART pinctrl setting without RTS/CTS, can be overwritten on
+  * board level if a different configuration is used.