From patchwork Thu Sep 17 15:26:56 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Lamparter X-Patchwork-Id: 518912 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from arrakis.dune.hu (arrakis.dune.hu [78.24.191.176]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 625F9140D83 for ; Fri, 18 Sep 2015 01:28:04 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=googlemail.com header.i=@googlemail.com header.b=ougurq97; dkim-atps=neutral Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id A8C1428755C; Thu, 17 Sep 2015 17:26:01 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on arrakis.dune.hu X-Spam-Level: X-Spam-Status: No, score=-1.5 required=5.0 tests=BAYES_00,FREEMAIL_FROM, T_DKIM_INVALID autolearn=unavailable version=3.3.2 Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id F026428749D for ; Thu, 17 Sep 2015 17:25:48 +0200 (CEST) X-policyd-weight: using cached result; rate: -8.5 Received: from mail-wi0-f181.google.com (mail-wi0-f181.google.com [209.85.212.181]) by arrakis.dune.hu (Postfix) with ESMTPS for ; Thu, 17 Sep 2015 17:25:46 +0200 (CEST) Received: by wicfx3 with SMTP id fx3so32299346wic.0 for ; Thu, 17 Sep 2015 08:26:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20120113; h=from:to:cc:subject:date:message-id:user-agent:mime-version :content-transfer-encoding:content-type; bh=Z0YBg4Fghb39xttB1n54HS07M6nHMHSUZrGcYyq3/1A=; b=ougurq97qEODCGBpJ7idXUrGzMZd4Aubz9ubHMdjgEOGZpEUtQe9Q2RQkzRJnkJCFv mEwuuQxIapfB+0AXBB8w7yPxeKeJHxPiUXLLx9A5q5QR0XYNf740977WkMAXBCYW7t9k UxN2dDaLK9MsUojgmmPW2WoWyxxIc+2i5AXnsnF8offeSAXQrPb70rORVRpRcfctInhw FoXNjs+9NaGUsxBnXYKJwElWmeRcTib/sh7i4XOKr2zgVoBwwaavic7kUcJXeIhvrgct ehzHaRi+LmKGoXfHEM+BuENMPVILzLNHLWGfgfVPEB0y7zii5F5Q+DPrzCXdsaQgtvbT ybxA== X-Received: by 10.194.62.48 with SMTP id v16mr2028115wjr.60.1442503617613; Thu, 17 Sep 2015 08:26:57 -0700 (PDT) Received: from debian64.daheim (pD9F8873C.dip0.t-ipconnect.de. [217.248.135.60]) by smtp.googlemail.com with ESMTPSA id fz1sm10613834wic.8.2015.09.17.08.26.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Sep 2015 08:26:57 -0700 (PDT) From: Chris R Blake X-Google-Original-From: Chris R Blake Received: from localhost.daheim ([127.0.0.1] helo=debian64.localnet) by debian64.daheim with esmtps (TLS1.0:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.86) (envelope-from ) id 1Zcb5M-00087L-Dd; Thu, 17 Sep 2015 17:26:56 +0200 To: openwrt-devel@lists.openwrt.org Date: Thu, 17 Sep 2015 17:26:56 +0200 Message-ID: <3601991.ABa55mtQhi@debian64> User-Agent: KMail/4.14.2 (Linux/4.3.0-rc1-wl+; KDE/4.14.10; x86_64; ; ) MIME-Version: 1.0 Subject: [OpenWrt-Devel] [PATCH v3 2/5] ar71xx: add support for qca955x sgmii/serdes calibration X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: openwrt-devel-bounces@lists.openwrt.org Sender: "openwrt-devel" From: Chris R Blake This patch is to add support for sgmii/serdes calibration from within the OpenWRT environment. This is needed on boards that do not use u-boot or do not have a pre-init process that runs calibration. Signed-off-by: Chris R Blake --- ...S-ath79-add-qca955x-mac-sgmii-calibration.patch | 82 ++++++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 target/linux/ar71xx/patches-4.1/743-MIPS-ath79-add-qca955x-mac-sgmii-calibration.patch diff --git a/target/linux/ar71xx/patches-4.1/743-MIPS-ath79-add-qca955x-mac-sgmii-calibration.patch b/target/linux/ar71xx/patches-4.1/743-MIPS-ath79-add-qca955x-mac-sgmii-calibration.patch new file mode 100644 index 0000000..eb7c5de --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/743-MIPS-ath79-add-qca955x-mac-sgmii-calibration.patch @@ -0,0 +1,82 @@ +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h 2015-08-05 12:58:15.580496899 +0200 ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h 2015-08-05 13:52:32.590857293 +0200 +@@ -360,6 +360,7 @@ + #define QCA955X_PLL_CLK_CTRL_REG 0x08 + #define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28 + #define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48 ++#define QCA955X_PLL_ETH_SGMII_SERDES_REG 0x4c + + #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 + #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +@@ -392,6 +393,10 @@ + #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) + #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + ++#define QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT BIT(2) ++#define QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK BIT(1) ++#define QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL BIT(0) ++ + #define QCA956X_PLL_CPU_CONFIG_REG 0x00 + #define QCA956X_PLL_CPU_CONFIG1_REG 0x04 + #define QCA956X_PLL_DDR_CONFIG_REG 0x08 +@@ -1104,5 +1109,11 @@ + #define QCA955X_ETH_CFG_RDV_DELAY BIT(16) + #define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3 + #define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16 ++ ++#define QCA955X_GMAC_REG_SGMII_SERDES 0x0018 ++#define QCA955X_SGMII_SERDES_RES_CALIBRATION BIT(23) ++#define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf ++#define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23 ++#define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15) + + #endif /* __ASM_MACH_AR71XX_REGS_H */ +--- a/arch/mips/ath79/dev-eth.c 2015-08-05 14:17:25.757504251 +0200 ++++ b/arch/mips/ath79/dev-eth.c 2015-08-05 14:09:54.716333554 +0200 +@@ -849,6 +849,37 @@ void __init ath79_setup_qca955x_eth_rx_d + iounmap(base); + } + ++void __init ath79_setup_qca955x_eth_serdes_cal(unsigned int sgmii_value) ++{ ++ void __iomem *ethbase, *pllbase; ++ u32 t; ++ ++ ethbase = ioremap_nocache(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE); ++ pllbase = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); ++ ++ /* To Check the locking of the SGMII PLL */ ++ t = __raw_readl(ethbase + QCA955X_GMAC_REG_SGMII_SERDES); ++ t &= ~(QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK << ++ QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT); ++ t |= (sgmii_value & QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK) << ++ QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT; ++ __raw_writel(t, ethbase + QCA955X_GMAC_REG_SGMII_SERDES); ++ ++ __raw_writel(QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT | ++ QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK | ++ QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL, ++ pllbase + QCA955X_PLL_ETH_SGMII_SERDES_REG); ++ ++ ath79_device_reset_clear(QCA955X_RESET_SGMII_ANALOG); ++ ath79_device_reset_clear(QCA955X_RESET_SGMII); ++ ++ while (!(__raw_readl(ethbase + QCA955X_GMAC_REG_SGMII_SERDES) & ++ QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS)); ++ ++ iounmap(ethbase); ++ iounmap(pllbase); ++} ++ + static int ath79_eth_instance __initdata; + void __init ath79_register_eth(unsigned int id) + { +--- a/arch/mips/ath79/dev-eth.h 2015-08-05 14:17:25.757504251 +0200 ++++ b/arch/mips/ath79/dev-eth.h 2015-08-05 13:58:20.292866210 +0200 +@@ -50,5 +50,6 @@ void ath79_setup_ar934x_eth_cfg(u32 mask + void ath79_setup_ar934x_eth_rx_delay(unsigned int rxd, unsigned int rxdv); + void ath79_setup_qca955x_eth_cfg(u32 mask); + void ath79_setup_qca955x_eth_rx_delay(unsigned int rxd, unsigned int rxdv); ++void ath79_setup_qca955x_eth_serdes_cal(unsigned int sgmii_value); + + #endif /* _ATH79_DEV_ETH_H */