new file mode 100644
@@ -0,0 +1,45 @@
+--- a/arch/mips/pci/ifxmips_pcie_vr9.h
++++ b/arch/mips/pci/ifxmips_pcie_vr9.h
+@@ -33,6 +33,7 @@
+ #define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */
+ #define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */
+ #define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */
++#define IFX_RCU_AHB_BE_XBAR_S 0x00000008 /* Configure AHB slave port that connects to XBAR in big endian */
+ #define CONFIG_IFX_PCIE_PHY_36MHZ_MODE
+
+ #define IFX_PMU1_MODULE_PCIE_PHY (0)
+--- a/arch/mips/pci/ifxmips_pcie.c
++++ b/arch/mips/pci/ifxmips_pcie.c
+@@ -51,6 +51,7 @@ static int pcie_reset_gpio;
+ static struct phy *ltq_pcie_phy;
+ static struct reset_control *ltq_pcie_reset;
+ static struct regmap *ltq_rcu_regmap;
++static bool switch_pcie_endianess;
+
+ static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = {
+ {
+@@ -1024,6 +1025,10 @@ pcie_rc_initialize(int pcie_port)
+ #ifdef CONFIG_IFX_PCIE_HW_SWAP
+ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S,
+ IFX_RCU_AHB_BE_PCIE_S);
++ if (switch_pcie_endianess) {
++ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_XBAR_S,
++ IFX_RCU_AHB_BE_XBAR_S);
++ }
+ #else
+ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S,
+ 0x0);
+@@ -1124,6 +1129,13 @@ static int ifx_pcie_bios_probe(struct pl
+ return PTR_ERR(ltq_pcie_phy);
+ }
+
++ if(of_property_read_bool(node, "lantiq,switch-pcie-endianess")) {
++ switch_pcie_endianess = true;
++ dev_info(&pdev->dev, "switch pcie endianess requested\n");
++ } else {
++ switch_pcie_endianess = false;
++ }
++
+ ltq_pcie_reset = devm_reset_control_get_shared(&pdev->dev, NULL);
+ if (IS_ERR(ltq_pcie_reset)) {
+ dev_err(&pdev->dev, "failed to get the PCIe reset line\n");
On some targets the AHB slave XBAR is wired up big endian. Allow specific targets to trigger a byte swap via a device tree property. Discussed in https://forum.openwrt.org/t/53620 Signed-off-by: Torsten Duwe <duwe@lst.de> --- I found this in Daniel's repo, merged into 0001-MIPS-lantiq-add-pcie-driver.patch, but I'd rather keep it separate, for clarity. The original commit message was lost in the merge; I wouldn't mind another signed-off by the original author ;-) --- ...q-ifxmips_pcie-fix-slave-XBAR-endian.patch | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 target/linux/lantiq/patches-5.10/0156-lantiq-ifxmips_pcie-fix-slave-XBAR-endian.patch