diff mbox series

[v7,2/2] mvebu: add support for iEi Puzzle-M901/Puzzle-M902

Message ID 20210830065221.5998-1-ianchang@ieiworld.com
State Superseded
Headers show
Series [v7,1/2] mvebu: backport CN9130 dts necessary files changes to 5.4 | expand

Commit Message

eveans2002@gmail.com Aug. 30, 2021, 6:52 a.m. UTC 
From: Ian Chang <ianchang@ieiworld.com>

 Hardware specification
 ----------------------
 * CN9130 SoC, Quad-core ARMv8 Cortex-72 @ 2200 MHz
 * 4 GB DDR
 * 4 GB eMMC
 * mmcblk0
 - mmcblk0p1    64M  kernel_1
 - mmcblk0p2    64M  kernel_2
 - mmcblk0p3   512M  rootfs_1
 - mmcblk0p4   512M  rootfs_2
 - mmcblk0p5   512M  Reserved
 - mmcblk0p6    64M  Reserved
 - mmcblk0p7   1.8G  rootfs_data

 * 4 MB (SPI Flash)
 * 6 x 2.5 Gigabit  ports (Puzzle-M901)
 - External PHY with 6 ports (AQR112R)

 * 6 x 2.5 Gigabit ports (Puzzle-M902)
 - External PHY with 6 ports (AQR112R)
   3 x 10 Gigabit ports (Puzzle-M902)
 - External PHY with 3 ports (AQR113R)

 * 4 x Front panel LED
 * 1 x USB 3.0
 * Reset button on Rear panel
 * UART (115200 8N1,header on PCB)

 Flash instructions:
    The original firmware is based on OpenWrt.
    Flash firmware using LuCI and CLI

Signed-off-by: Ian Chang <ianchang@ieiworld.com>
---
 .../base-files/etc/board.d/02_network         |   6 +
 .../cortexa72/base-files/lib/upgrade/emmc.sh  |  36 ++
 .../base-files/lib/upgrade/platform.sh        |   8 +
 .../boot/dts/marvell/cn9131-puzzle-m901.dts   | 319 ++++++++++++
 .../boot/dts/marvell/cn9132-puzzle-m902.dts   | 481 ++++++++++++++++++
 target/linux/mvebu/image/cortexa72.mk         |  18 +
 6 files changed, 868 insertions(+)
 create mode 100644 target/linux/mvebu/cortexa72/base-files/lib/upgrade/emmc.sh
 create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts
 create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts

Comments

Daniel Golle Sept. 1, 2021, 12:18 a.m. UTC | #1 
Hi Ian,

I just tried pulling this into my staging tree and unfortunately the
patch no longer applies cleanly:

Applying: mvebu: add support for iEi Puzzle-M901/Puzzle-M902
warning: target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network has type 100644, expected 100755
error: patch failed: target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh:9
error: target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh: patch does not apply
Patch failed at 0002 mvebu: add support for iEi Puzzle-M901/Puzzle-M902
hint: Use 'git am --show-current-patch=diff' to see the failed patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

Please rebase and fix the patch so that it applies on top of the
current openwrt.git master branch (probably just some minor issue as
the patch applies with some fuzz when applying manually. Yet it should
be tested on the hardware to make sure nothing got damaged by other
changes in the meantime, which are the cause for the patch not applying
cleanly any longer).

Also, adding the 'emmc.sh' file with it's current name 'emmc.sh'
suggests that it would be somehow generic.
However, it contains hard-coded partitions specific for the Puzzle
devices and it would be better to also reflect that in the filename,
e.g. call it 'emmc-puzzle.sh'.

That being said, I do like that eMMC dual-boot layout, no single point
of failed, no legacy MSDOS/FAT partition: that's wonderful (and better
than most vendor-provided bootchain setups I have seen until now)!

Please give this a quick respin so we finally get this merged.


Cheers



Daniel


On Mon, Aug 30, 2021 at 02:52:21PM +0800, eveans2002@gmail.com wrote:
> From: Ian Chang <ianchang@ieiworld.com>
> 
>  Hardware specification
>  ----------------------
>  * CN9130 SoC, Quad-core ARMv8 Cortex-72 @ 2200 MHz
>  * 4 GB DDR
>  * 4 GB eMMC
>  * mmcblk0
>  - mmcblk0p1    64M  kernel_1
>  - mmcblk0p2    64M  kernel_2
>  - mmcblk0p3   512M  rootfs_1
>  - mmcblk0p4   512M  rootfs_2
>  - mmcblk0p5   512M  Reserved
>  - mmcblk0p6    64M  Reserved
>  - mmcblk0p7   1.8G  rootfs_data
> 
>  * 4 MB (SPI Flash)
>  * 6 x 2.5 Gigabit  ports (Puzzle-M901)
>  - External PHY with 6 ports (AQR112R)
> 
>  * 6 x 2.5 Gigabit ports (Puzzle-M902)
>  - External PHY with 6 ports (AQR112R)
>    3 x 10 Gigabit ports (Puzzle-M902)
>  - External PHY with 3 ports (AQR113R)
> 
>  * 4 x Front panel LED
>  * 1 x USB 3.0
>  * Reset button on Rear panel
>  * UART (115200 8N1,header on PCB)
> 
>  Flash instructions:
>     The original firmware is based on OpenWrt.
>     Flash firmware using LuCI and CLI
> 
> Signed-off-by: Ian Chang <ianchang@ieiworld.com>
> ---
>  .../base-files/etc/board.d/02_network         |   6 +
>  .../cortexa72/base-files/lib/upgrade/emmc.sh  |  36 ++
>  .../base-files/lib/upgrade/platform.sh        |   8 +
>  .../boot/dts/marvell/cn9131-puzzle-m901.dts   | 319 ++++++++++++
>  .../boot/dts/marvell/cn9132-puzzle-m902.dts   | 481 ++++++++++++++++++
>  target/linux/mvebu/image/cortexa72.mk         |  18 +
>  6 files changed, 868 insertions(+)
>  create mode 100644 target/linux/mvebu/cortexa72/base-files/lib/upgrade/emmc.sh
>  create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts
>  create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts
> 
> diff --git a/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network b/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network
> index 9ab3c8174d..e0a4bc3015 100755
> --- a/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network
> +++ b/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network
> @@ -11,6 +11,12 @@ board_config_update
>  board=$(board_name)
>  
>  case "$board" in
> +iei,puzzle-m901)
> +	ucidef_set_interfaces_lan_wan "eth1 eth2 eth3 eth4 eth5" "eth0"
> +	;;
> +iei,puzzle-m902)
> +	ucidef_set_interfaces_lan_wan "eth1 eth2 eth3 eth4 eth5 eth10 eth11 eth12" "eth0"
> +	;;
>  marvell,armada8040-mcbin-doubleshot|\
>  marvell,armada8040-mcbin-singleshot)
>  	ucidef_set_interfaces_lan_wan "eth0 eth1 eth3" "eth2"
> diff --git a/target/linux/mvebu/cortexa72/base-files/lib/upgrade/emmc.sh b/target/linux/mvebu/cortexa72/base-files/lib/upgrade/emmc.sh
> new file mode 100644
> index 0000000000..5e5c356ed6
> --- /dev/null
> +++ b/target/linux/mvebu/cortexa72/base-files/lib/upgrade/emmc.sh
> @@ -0,0 +1,36 @@
> +platform_do_upgrade_emmc() {
> +	local board=$(board_name)
> +	local diskdev partdev
> +
> +	export_bootdevice && export_partdevice diskdev 0 || {
> +		v "Unable to determine upgrade device"
> +		return 1
> +	}
> +	sync
> +	if [ "$UPGRADE_OPT_SAVE_PARTITIONS" = "1" ]; then
> +		get_partitions "/dev/$diskdev" bootdisk
> +		v "Extract boot sector from the image"
> +		get_image_dd "$1" of=/tmp/image.bs count=1 bs=512b
> +		get_partitions /tmp/image.bs image
> +	fi
> +
> +	#iterate over each partition from the image and write it to the boot disk
> +	while read part start size; do
> +		if export_partdevice partdev $part; then
> +			if [ "$partdev" = "mmcblk0p2" ]; then
> +				v "Writing image mmcblk0p3 for /dev/$partdev  $start $size"
> +				get_image_dd "$1" of="/dev/mmcblk0p3" ibs="512" obs=1M skip="$start" count="$size" conv=fsync
> +			elif [ "$partdev" = "mmcblk0p1" ]; then
> +				v "Writing image mmcblk0p1 for /dev/$partdev $start $size"
> +				get_image_dd "$1" of="/dev/$partdev" ibs="512" obs=1M skip="$start" count="$size" conv=fsync
> +			fi
> +		else
> +			v "Unable to find partition $part device, skipped."
> +		fi
> +	done < /tmp/partmap.image
> +
> +	v "Writing new UUID to /dev/$diskdev..."
> +	get_image_dd "$1" of="/dev/$diskdev" bs=1 skip=440 count=4 seek=440 conv=fsync
> +
> +	sleep 1
> +}
> diff --git a/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh b/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh
> index 04ea634097..9a89768d14 100755
> --- a/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh
> +++ b/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh
> @@ -9,6 +9,8 @@ REQUIRE_IMAGE_METADATA=1
>  
>  platform_check_image() {
>  	case "$(board_name)" in
> +	iei,puzzle-m901|\
> +	iei,puzzle-m902|\
>  	marvell,armada8040-mcbin-doubleshot|\
>  	marvell,armada8040-mcbin-singleshot)
>  		platform_check_image_sdcard "$1"
> @@ -21,6 +23,10 @@ platform_check_image() {
>  
>  platform_do_upgrade() {
>  	case "$(board_name)" in
> +	iei,puzzle-m901|\
> +	iei,puzzle-m902)
> +		platform_do_upgrade_emmc "$1"
> +		;;
>  	marvell,armada8040-mcbin-doubleshot|\
>  	marvell,armada8040-mcbin-singleshot)
>  		platform_do_upgrade_sdcard "$1"
> @@ -32,6 +38,8 @@ platform_do_upgrade() {
>  }
>  platform_copy_config() {
>  	case "$(board_name)" in
> +	iei,puzzle-m901|\
> +	iei,puzzle-m902|\
>  	marvell,armada8040-mcbin-doubleshot|\
>  	marvell,armada8040-mcbin-singleshot)
>  		platform_copy_config_sdcard
> diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts
> new file mode 100644
> index 0000000000..58e749490a
> --- /dev/null
> +++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts
> @@ -0,0 +1,319 @@
> +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
> +/*
> + * Copyright (C) 2019 Marvell International Ltd.
> + *
> + * Device tree for the CN9131-DB board.
> + */
> +
> +#include "cn9130.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> +	model = "iEi Puzzle-M901";
> +	compatible = "iei,puzzle-m901",
> +		     "marvell,armada-ap807-quad", "marvell,armada-ap807";
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	aliases {
> +		i2c0 = &cp1_i2c0;
> +		i2c1 = &cp0_i2c0;
> +		ethernet0 = &cp0_eth0;
> +		ethernet1 = &cp0_eth1;
> +		ethernet2 = &cp0_eth2;
> +		ethernet3 = &cp1_eth0;
> +		ethernet4 = &cp1_eth1;
> +		ethernet5 = &cp1_eth2;
> +		gpio1 = &cp0_gpio1;
> +		gpio2 = &cp0_gpio2;
> +		gpio3 = &cp1_gpio1;
> +		gpio4 = &cp1_gpio2;
> +	};
> +
> +	memory@00000000 {
> +		device_type = "memory";
> +		reg = <0x0 0x0 0x0 0x80000000>;
> +	};
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> +
> +&cp0_uart0 {
> +	status = "okay";
> +};
> +
> +/* on-board eMMC - U9 */
> +&ap_sdhci0 {
> +	pinctrl-names = "default";
> +	bus-width = <8>;
> +	status = "okay";
> +	mmc-ddr-1_8v;
> +	mmc-hs400-1_8v;
> +};
> +
> +&cp0_crypto {
> +	status = "okay";
> +};
> +
> +&cp0_xmdio {
> +	status = "okay";
> +	cp0_nbaset_phy0: ethernet-phy@0 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <2>;
> +	};
> +	cp0_nbaset_phy1: ethernet-phy@1 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <0>;
> +	};
> +	cp0_nbaset_phy2: ethernet-phy@2 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <8>;
> +	};
> +};
> +
> +&cp0_ethernet {
> +	status = "okay";
> +};
> +
> +/* SLM-1521-V2, CON9 */
> +&cp0_eth0 {
> +	status = "okay";
> +	phy-mode = "2500base-x";
> +	phys = <&cp0_comphy2 0>;
> +	managed = "in-band-status";
> +};
> +
> +&cp0_eth1 {
> +	status = "okay";
> +	phy-mode = "2500base-x";
> +	phys = <&cp0_comphy4 1>;
> +	managed = "in-band-status";
> +};
> +
> +&cp0_eth2 {
> +	status = "okay";
> +	phy-mode = "2500base-x";
> +	phys = <&cp0_comphy5 2>;
> +	managed = "in-band-status";
> +};
> +
> +&cp0_gpio1 {
> +	status = "okay";
> +};
> +
> +&cp0_gpio2 {
> +	status = "okay";
> +};
> +
> +&cp0_i2c0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&cp0_i2c0_pins>;
> +	status = "okay";
> +	clock-frequency = <100000>;
> +	rtc@32 {
> +		compatible = "epson,rx8130";
> +		reg = <0x32>;
> +		wakeup-source;
> +	};
> +};
> +
> +/* SLM-1521-V2, CON6 */
> +&cp0_pcie0 {
> +	status = "okay";
> +	num-lanes = <2>;
> +	num-viewport = <8>;
> +	phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>;
> +};
> +
> +/* U55 */
> +&cp0_spi1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&cp0_spi0_pins>;
> +	reg = <0x700680 0x50>,          /* control */
> +	      <0x2000000 0x1000000>;    /* CS0 */
> +	status = "okay";
> +	spi-flash@0 {
> +		#address-cells = <0x1>;
> +		#size-cells = <0x1>;
> +		compatible = "jedec,spi-nor";
> +		reg = <0x0>;
> +		spi-max-frequency = <40000000>;
> +		partitions {
> +			compatible = "fixed-partitions";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			partition@0 {
> +				label = "U-Boot";
> +				reg = <0x0 0x1f0000>;
> +			};
> +			partition@1f0000 {
> +				label = "U-Boot ENV Factory";
> +				reg = <0x1f0000 0x10000>;
> +			};
> +			partition@200000 {
> +				label = "Reserved";
> +				reg = <0x200000 0x1f0000>;
> +			};
> +			partition@3f0000 {
> +				label = "U-Boot ENV";
> +				reg = <0x3f0000 0x10000>;
> +			};
> +		};
> +	};
> +};
> +
> +&cp0_syscon0 {
> +	cp0_pinctrl: pinctrl {
> +		compatible = "marvell,cp115-standalone-pinctrl";
> +		cp0_i2c0_pins: cp0-i2c-pins-0 {
> +			marvell,pins = "mpp37", "mpp38";
> +			marvell,function = "i2c0";
> +		};
> +		cp0_i2c1_pins: cp0-i2c-pins-1 {
> +			marvell,pins = "mpp35", "mpp36";
> +			marvell,function = "i2c1";
> +		};
> +		cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
> +			marvell,pins = "mpp0", "mpp1", "mpp2",
> +				       "mpp3", "mpp4", "mpp5",
> +				       "mpp6", "mpp7", "mpp8",
> +				       "mpp9", "mpp10", "mpp11";
> +			marvell,function = "ge0";
> +		};
> +		cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
> +			marvell,pins = "mpp44", "mpp45", "mpp46",
> +				       "mpp47", "mpp48", "mpp49",
> +				       "mpp50", "mpp51", "mpp52",
> +				       "mpp53", "mpp54", "mpp55";
> +			marvell,function = "ge1";
> +		};
> +		cp0_spi0_pins: cp0-spi-pins-0 {
> +			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
> +			marvell,function = "spi1";
> +		};
> +	};
> +};
> +
> +/*
> + * Instantiate the first connected CP115
> + */
> +
> +#define CP11X_NAME		cp1
> +#define CP11X_BASE		f6000000
> +#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
> +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
> +#define CP11X_PCIE0_BASE	f6600000
> +#define CP11X_PCIE1_BASE	f6620000
> +#define CP11X_PCIE2_BASE	f6640000
> +
> +#include "armada-cp115.dtsi"
> +
> +#undef CP11X_NAME
> +#undef CP11X_BASE
> +#undef CP11X_PCIEx_MEM_BASE
> +#undef CP11X_PCIEx_MEM_SIZE
> +#undef CP11X_PCIE0_BASE
> +#undef CP11X_PCIE1_BASE
> +#undef CP11X_PCIE2_BASE
> +
> +&cp1_crypto {
> +	status = "okay";
> +};
> +
> +&cp1_xmdio {
> +	status = "okay";
> +	cp1_nbaset_phy0: ethernet-phy@3 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <2>;
> +	};
> +	cp1_nbaset_phy1: ethernet-phy@4 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <0>;
> +	};
> +	cp1_nbaset_phy2: ethernet-phy@5 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <8>;
> +	};
> +};
> +
> +&cp1_ethernet {
> +	status = "okay";
> +};
> +
> +/* CON50 */
> +&cp1_eth0 {
> +	status = "okay";
> +	phy-mode = "2500base-x";
> +	phys = <&cp1_comphy2 0>;
> +	managed = "in-band-status";
> +};
> +
> +&cp1_eth1 {
> +	status = "okay";
> +	phy-mode = "2500base-x";
> +	phys = <&cp1_comphy4 1>;
> +	managed = "in-band-status";
> +};
> +
> +&cp1_eth2 {
> +	status = "okay";
> +	phy-mode = "2500base-x";
> +	phys = <&cp1_comphy5 2>;
> +	managed = "in-band-status";
> +};
> +
> +&cp1_sata0 {
> +	status = "okay";
> +	sata-port@1 {
> +		status = "okay";
> +		phys = <&cp1_comphy0 1>;
> +	};
> +};
> +
> +&cp1_gpio1 {
> +	status = "okay";
> +};
> +
> +&cp1_gpio2 {
> +	status = "okay";
> +};
> +
> +&cp1_i2c0 {
> +	status = "okay";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&cp1_i2c0_pins>;
> +	clock-frequency = <100000>;
> +};
> +
> +&cp1_syscon0 {
> +	cp1_pinctrl: pinctrl {
> +		compatible = "marvell,cp115-standalone-pinctrl";
> +		cp1_i2c0_pins: cp1-i2c-pins-0 {
> +			marvell,pins = "mpp37", "mpp38";
> +			marvell,function = "i2c0";
> +		};
> +		cp1_spi0_pins: cp1-spi-pins-0 {
> +			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
> +			marvell,function = "spi1";
> +		};
> +		cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
> +			marvell,pins = "mpp3";
> +			marvell,function = "gpio";
> +		};
> +		cp1_sfp_pins: sfp-pins {
> +			marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
> +			marvell,function = "gpio";
> +		};
> +	};
> +};
> +
> +&cp1_usb3_1 {
> +	status = "okay";
> +	phys = <&cp1_comphy3 1>;
> +	phy-names = "usb";
> +};
> diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts
> new file mode 100644
> index 0000000000..dc4e6527f1
> --- /dev/null
> +++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts
> @@ -0,0 +1,481 @@
> +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
> +/*
> + * Copyright (C) 2019 Marvell International Ltd.
> + *
> + * Device tree for the CN9132-DB board.
> + */
> +
> +#include "cn9130.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> +	model = "iEi Puzzle-M902";
> +	compatible = "iei,puzzle-m902",
> +		     "marvell,armada-ap807-quad", "marvell,armada-ap807";
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	aliases {
> +		i2c0 = &cp1_i2c0;
> +		i2c1 = &cp0_i2c0;
> +		gpio1 = &cp0_gpio1;
> +		gpio2 = &cp0_gpio2;
> +		gpio3 = &cp1_gpio1;
> +		gpio4 = &cp1_gpio2;
> +		gpio5 = &cp2_gpio1;
> +		gpio6 = &cp2_gpio2;
> +		ethernet0 = &cp0_eth0;
> +		ethernet1 = &cp0_eth1;
> +		ethernet2 = &cp0_eth2;
> +		ethernet3 = &cp1_eth0;
> +		ethernet4 = &cp1_eth1;
> +		ethernet5 = &cp1_eth2;
> +		ethernet6 = &cp2_eth0;
> +		ethernet7 = &cp2_eth1;
> +		ethernet8 = &cp2_eth2;
> +		spi1 = &cp0_spi0;
> +		spi2 = &cp0_spi1;
> +		serial1 = &cp0_uart0;
> +	};
> +
> +	memory@00000000 {
> +		device_type = "memory";
> +		reg = <0x0 0x0 0x0 0x80000000>;
> +	};
> +
> +	cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "cp2-xhci0-vbus";
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +		enable-active-high;
> +		gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
> +	};
> +
> +	cp2_usb3_0_phy0: cp2_usb3_phy0 {
> +		compatible = "usb-nop-xceiv";
> +		vcc-supply = <&cp2_reg_usb3_vbus0>;
> +	};
> +
> +	cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "cp2-xhci1-vbus";
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +		enable-active-high;
> +		gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
> +	};
> +
> +	cp2_usb3_0_phy1: cp2_usb3_phy1 {
> +		compatible = "usb-nop-xceiv";
> +		vcc-supply = <&cp2_reg_usb3_vbus1>;
> +	};
> +
> +	cp2_sfp_eth0: sfp-eth0 {
> +		compatible = "sff,sfp";
> +		i2c-bus = <&cp2_sfpp0_i2c>;
> +		los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
> +		mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
> +		tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
> +		tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
> +		status = "disabled";
> +	};
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> +
> +&cp0_uart0 {
> +	status = "okay";
> +};
> +
> +/* on-board eMMC - U9 */
> +&ap_sdhci0 {
> +	pinctrl-names = "default";
> +	bus-width = <8>;
> +	status = "okay";
> +	mmc-ddr-1_8v;
> +	mmc-hs400-1_8v;
> +};
> +
> +&cp0_crypto {
> +	status = "okay";
> +};
> +
> +&cp0_xmdio {
> +	status = "okay";
> +	cp0_nbaset_phy0: ethernet-phy@0 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <2>;
> +	};
> +	cp0_nbaset_phy1: ethernet-phy@1 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <0>;
> +	};
> +	cp0_nbaset_phy2: ethernet-phy@2 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <8>;
> +	};
> +};
> +
> +&cp0_ethernet {
> +	status = "okay";
> +};
> +
> +/* SLM-1521-V2, CON9 */
> +&cp0_eth0 {
> +	status = "okay";
> +	phy-mode = "10gbase-kr";
> +	phys = <&cp0_comphy2 0>;
> +	managed = "in-band-status";
> +};
> +
> +&cp0_eth1 {
> +	status = "okay";
> +	phy-mode = "2500base-x";
> +	phys = <&cp0_comphy4 1>;
> +	managed = "in-band-status";
> +};
> +
> +&cp0_eth2 {
> +	status = "okay";
> +	phy-mode = "2500base-x";
> +	phys = <&cp0_comphy1 2>;
> +	managed = "in-band-status";
> +};
> +
> +&cp0_gpio1 {
> +	status = "okay";
> +};
> +
> +&cp0_gpio2 {
> +	status = "okay";
> +};
> +
> +&cp0_i2c0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&cp0_i2c0_pins>;
> +	status = "okay";
> +	clock-frequency = <100000>;
> +	rtc@32 {
> +		compatible = "epson,rx8130";
> +		reg = <0x32>;
> +		wakeup-source;
> +	};
> +};
> +
> +&cp0_i2c1 {
> +	clock-frequency = <100000>;
> +};
> +
> +/* SLM-1521-V2, CON6 */
> +&cp0_sata0 {
> +	status = "okay";
> +	sata-port@1 {
> +		status = "okay";
> +		phys = <&cp0_comphy0 1>;
> +	};
> +};
> +
> +&cp0_pcie2 {
> +	status = "okay";
> +	num-lanes = <1>;
> +	num-viewport = <8>;
> +	phys = <&cp0_comphy5 2>;
> +};
> +
> +/* U55 */
> +&cp0_spi1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&cp0_spi0_pins>;
> +	reg = <0x700680 0x50>,          /* control */
> +	      <0x2000000 0x1000000>;    /* CS0 */
> +	status = "okay";
> +	spi-flash@0 {
> +		#address-cells = <0x1>;
> +		#size-cells = <0x1>;
> +		compatible = "jedec,spi-nor";
> +		reg = <0x0>;
> +		spi-max-frequency = <40000000>;
> +		partitions {
> +			compatible = "fixed-partitions";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			partition@0 {
> +				label = "U-Boot";
> +				reg = <0x0 0x1f0000>;
> +			};
> +			partition@1f0000 {
> +				label = "U-Boot ENV Factory";
> +				reg = <0x1f0000 0x10000>;
> +			};
> +			partition@200000 {
> +				label = "Reserved";
> +				reg = <0x200000 0x1f0000>;
> +			};
> +			partition@3f0000 {
> +				label = "U-Boot ENV";
> +				reg = <0x3f0000 0x10000>;
> +			};
> +		};
> +	};
> +};
> +
> +&cp0_syscon0 {
> +	cp0_pinctrl: pinctrl {
> +		compatible = "marvell,cp115-standalone-pinctrl";
> +		cp0_i2c0_pins: cp0-i2c-pins-0 {
> +			marvell,pins = "mpp37", "mpp38";
> +			marvell,function = "i2c0";
> +		};
> +		cp0_i2c1_pins: cp0-i2c-pins-1 {
> +			marvell,pins = "mpp35", "mpp36";
> +			marvell,function = "i2c1";
> +		};
> +		cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
> +			marvell,pins = "mpp0", "mpp1", "mpp2",
> +				       "mpp3", "mpp4", "mpp5",
> +				       "mpp6", "mpp7", "mpp8",
> +				       "mpp9", "mpp10", "mpp11";
> +			marvell,function = "ge0";
> +		};
> +		cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
> +			marvell,pins = "mpp44", "mpp45", "mpp46",
> +				       "mpp47", "mpp48", "mpp49",
> +				       "mpp50", "mpp51", "mpp52",
> +				       "mpp53", "mpp54", "mpp55";
> +			marvell,function = "ge1";
> +		};
> +		cp0_spi0_pins: cp0-spi-pins-0 {
> +			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
> +			marvell,function = "spi1";
> +		};
> +	};
> +};
> +
> +&cp0_usb3_1 {
> +	status = "okay";
> +	phys = <&cp0_comphy3 1>;
> +	phy-names = "usb";
> +};
> +
> +/*
> + * Instantiate the first connected CP115
> + */
> +
> +#define CP11X_NAME		cp1
> +#define CP11X_BASE		f4000000
> +#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
> +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
> +#define CP11X_PCIE0_BASE	f4600000
> +#define CP11X_PCIE1_BASE	f4620000
> +#define CP11X_PCIE2_BASE	f4640000
> +
> +#include "armada-cp115.dtsi"
> +
> +#undef CP11X_NAME
> +#undef CP11X_BASE
> +#undef CP11X_PCIEx_MEM_BASE
> +#undef CP11X_PCIEx_MEM_SIZE
> +#undef CP11X_PCIE0_BASE
> +#undef CP11X_PCIE1_BASE
> +#undef CP11X_PCIE2_BASE
> +
> +&cp1_crypto {
> +	status = "okay";
> +};
> +
> +&cp1_xmdio {
> +	status = "okay";
> +	cp1_nbaset_phy0: ethernet-phy@3 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <2>;
> +	};
> +	cp1_nbaset_phy1: ethernet-phy@4 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <0>;
> +	};
> +	cp1_nbaset_phy2: ethernet-phy@5 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <8>;
> +	};
> +};
> +
> +&cp1_ethernet {
> +	status = "okay";
> +};
> +
> +/* CON50 */
> +&cp1_eth0 {
> +	status = "okay";
> +	phy-mode = "10gbase-kr";
> +	phys = <&cp1_comphy2 0>;
> +	managed = "in-band-status";
> +};
> +
> +&cp1_eth1 {
> +	status = "okay";
> +	phy-mode = "2500base-x";
> +	phys = <&cp1_comphy4 1>;
> +	managed = "in-band-status";
> +};
> +
> +&cp1_eth2 {
> +	status = "okay";
> +	phy-mode = "2500base-x";
> +	phys = <&cp1_comphy1 2>;
> +	managed = "in-band-status";
> +};
> +
> +&cp1_gpio1 {
> +	status = "okay";
> +};
> +
> +&cp1_gpio2 {
> +	status = "okay";
> +};
> +
> +&cp1_i2c0 {
> +	status = "okay";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&cp1_i2c0_pins>;
> +	clock-frequency = <100000>;
> +};
> +
> +&cp1_syscon0 {
> +	cp1_pinctrl: pinctrl {
> +		compatible = "marvell,cp115-standalone-pinctrl";
> +		cp1_i2c0_pins: cp1-i2c-pins-0 {
> +			marvell,pins = "mpp37", "mpp38";
> +			marvell,function = "i2c0";
> +		};
> +		cp1_spi0_pins: cp1-spi-pins-0 {
> +			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
> +			marvell,function = "spi1";
> +		};
> +		cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
> +			marvell,pins = "mpp3";
> +			marvell,function = "gpio";
> +		};
> +	};
> +};
> +
> +/*
> + * Instantiate the second connected CP115
> + */
> +
> +#define CP11X_NAME		cp2
> +#define CP11X_BASE		f6000000
> +#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
> +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
> +#define CP11X_PCIE0_BASE	f6600000
> +#define CP11X_PCIE1_BASE	f6620000
> +#define CP11X_PCIE2_BASE	f6640000
> +
> +#include "armada-cp115.dtsi"
> +
> +#undef CP11X_NAME
> +#undef CP11X_BASE
> +#undef CP11X_PCIEx_MEM_BASE
> +#undef CP11X_PCIEx_MEM_SIZE
> +#undef CP11X_PCIE0_BASE
> +#undef CP11X_PCIE1_BASE
> +#undef CP11X_PCIE2_BASE
> +
> +&cp2_crypto {
> +	status = "okay";
> +};
> +
> +&cp2_ethernet {
> +	status = "okay";
> +};
> +
> +&cp2_xmdio {
> +	status = "okay";
> +	cp2_nbaset_phy0: ethernet-phy@6 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <2>;
> +	};
> +	cp2_nbaset_phy1: ethernet-phy@7 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <0>;
> +	};
> +	cp2_nbaset_phy2: ethernet-phy@8 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <8>;
> +	};
> +};
> +
> +/* SLM-1521-V2, CON9 */
> +&cp2_eth0 {
> +	status = "okay";
> +	phy-mode = "10gbase-kr";
> +	phys = <&cp2_comphy2 0>;
> +	managed = "in-band-status";
> +};
> +
> +&cp2_eth1 {
> +	status = "okay";
> +	phy-mode = "2500base-x";
> +	phys = <&cp2_comphy4 1>;
> +	managed = "in-band-status";
> +};
> +
> +&cp2_eth2 {
> +	status = "okay";
> +	phy-mode = "2500base-x";
> +	phys = <&cp2_comphy1 2>;
> +	managed = "in-band-status";
> +};
> +
> +&cp2_gpio1 {
> +	status = "okay";
> +};
> +
> +&cp2_gpio2 {
> +	status = "okay";
> +};
> +
> +&cp2_i2c0 {
> +	clock-frequency = <100000>;
> +	/* SLM-1521-V2 - U3 */
> +	i2c-mux@72 {
> +		compatible = "nxp,pca9544";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		reg = <0x72>;
> +		cp2_sfpp0_i2c: i2c@0 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0>;
> +		};
> +
> +		i2c@1 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <1>;
> +			/* U12 */
> +			cp2_module_expander1: pca9555@21 {
> +				compatible = "nxp,pca9555";
> +				pinctrl-names = "default";
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				reg = <0x21>;
> +			};
> +		};
> +	};
> +};
> +
> +&cp2_syscon0 {
> +	cp2_pinctrl: pinctrl {
> +		compatible = "marvell,cp115-standalone-pinctrl";
> +		cp2_i2c0_pins: cp2-i2c-pins-0 {
> +			marvell,pins = "mpp37", "mpp38";
> +			marvell,function = "i2c0";
> +		};
> +	};
> +};
> diff --git a/target/linux/mvebu/image/cortexa72.mk b/target/linux/mvebu/image/cortexa72.mk
> index 1440c07a0b..29727f8b9d 100644
> --- a/target/linux/mvebu/image/cortexa72.mk
> +++ b/target/linux/mvebu/image/cortexa72.mk
> @@ -43,3 +43,21 @@ define Device/marvell_macchiatobin-singleshot
>    SUPPORTED_DEVICES := marvell,armada8040-mcbin-singleshot
>  endef
>  TARGET_DEVICES += marvell_macchiatobin-singleshot
> +
> +define Device/iei_puzzle-m901
> +  $(call Device/Default-arm64)
> +  DEVICE_VENDOR := iEi
> +  DEVICE_MODEL := Puzzle-M901
> +  SOC := cn9131
> +  IMAGE/sdcard.img.gz := boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata
> +endef
> +TARGET_DEVICES += iei_puzzle-m901
> +
> +define Device/iei_puzzle-m902
> +  $(call Device/Default-arm64)
> +  DEVICE_VENDOR := iEi
> +  DEVICE_MODEL := Puzzle-M902
> +  SOC := cn9132
> +  IMAGE/sdcard.img.gz := boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata
> +endef
> +TARGET_DEVICES += iei_puzzle-m902
> -- 
> 2.17.1
> 
> 
> _______________________________________________
> openwrt-devel mailing list
> openwrt-devel@lists.openwrt.org
> https://lists.openwrt.org/mailman/listinfo/openwrt-devel
diff mbox series

Patch

diff --git a/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network b/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network
index 9ab3c8174d..e0a4bc3015 100755
--- a/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network
+++ b/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network
@@ -11,6 +11,12 @@  board_config_update
 board=$(board_name)
 
 case "$board" in
+iei,puzzle-m901)
+	ucidef_set_interfaces_lan_wan "eth1 eth2 eth3 eth4 eth5" "eth0"
+	;;
+iei,puzzle-m902)
+	ucidef_set_interfaces_lan_wan "eth1 eth2 eth3 eth4 eth5 eth10 eth11 eth12" "eth0"
+	;;
 marvell,armada8040-mcbin-doubleshot|\
 marvell,armada8040-mcbin-singleshot)
 	ucidef_set_interfaces_lan_wan "eth0 eth1 eth3" "eth2"
diff --git a/target/linux/mvebu/cortexa72/base-files/lib/upgrade/emmc.sh b/target/linux/mvebu/cortexa72/base-files/lib/upgrade/emmc.sh
new file mode 100644
index 0000000000..5e5c356ed6
--- /dev/null
+++ b/target/linux/mvebu/cortexa72/base-files/lib/upgrade/emmc.sh
@@ -0,0 +1,36 @@ 
+platform_do_upgrade_emmc() {
+	local board=$(board_name)
+	local diskdev partdev
+
+	export_bootdevice && export_partdevice diskdev 0 || {
+		v "Unable to determine upgrade device"
+		return 1
+	}
+	sync
+	if [ "$UPGRADE_OPT_SAVE_PARTITIONS" = "1" ]; then
+		get_partitions "/dev/$diskdev" bootdisk
+		v "Extract boot sector from the image"
+		get_image_dd "$1" of=/tmp/image.bs count=1 bs=512b
+		get_partitions /tmp/image.bs image
+	fi
+
+	#iterate over each partition from the image and write it to the boot disk
+	while read part start size; do
+		if export_partdevice partdev $part; then
+			if [ "$partdev" = "mmcblk0p2" ]; then
+				v "Writing image mmcblk0p3 for /dev/$partdev  $start $size"
+				get_image_dd "$1" of="/dev/mmcblk0p3" ibs="512" obs=1M skip="$start" count="$size" conv=fsync
+			elif [ "$partdev" = "mmcblk0p1" ]; then
+				v "Writing image mmcblk0p1 for /dev/$partdev $start $size"
+				get_image_dd "$1" of="/dev/$partdev" ibs="512" obs=1M skip="$start" count="$size" conv=fsync
+			fi
+		else
+			v "Unable to find partition $part device, skipped."
+		fi
+	done < /tmp/partmap.image
+
+	v "Writing new UUID to /dev/$diskdev..."
+	get_image_dd "$1" of="/dev/$diskdev" bs=1 skip=440 count=4 seek=440 conv=fsync
+
+	sleep 1
+}
diff --git a/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh b/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh
index 04ea634097..9a89768d14 100755
--- a/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh
+++ b/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh
@@ -9,6 +9,8 @@  REQUIRE_IMAGE_METADATA=1
 
 platform_check_image() {
 	case "$(board_name)" in
+	iei,puzzle-m901|\
+	iei,puzzle-m902|\
 	marvell,armada8040-mcbin-doubleshot|\
 	marvell,armada8040-mcbin-singleshot)
 		platform_check_image_sdcard "$1"
@@ -21,6 +23,10 @@  platform_check_image() {
 
 platform_do_upgrade() {
 	case "$(board_name)" in
+	iei,puzzle-m901|\
+	iei,puzzle-m902)
+		platform_do_upgrade_emmc "$1"
+		;;
 	marvell,armada8040-mcbin-doubleshot|\
 	marvell,armada8040-mcbin-singleshot)
 		platform_do_upgrade_sdcard "$1"
@@ -32,6 +38,8 @@  platform_do_upgrade() {
 }
 platform_copy_config() {
 	case "$(board_name)" in
+	iei,puzzle-m901|\
+	iei,puzzle-m902|\
 	marvell,armada8040-mcbin-doubleshot|\
 	marvell,armada8040-mcbin-singleshot)
 		platform_copy_config_sdcard
diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts
new file mode 100644
index 0000000000..58e749490a
--- /dev/null
+++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts
@@ -0,0 +1,319 @@ 
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * Device tree for the CN9131-DB board.
+ */
+
+#include "cn9130.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "iEi Puzzle-M901";
+	compatible = "iei,puzzle-m901",
+		     "marvell,armada-ap807-quad", "marvell,armada-ap807";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		i2c0 = &cp1_i2c0;
+		i2c1 = &cp0_i2c0;
+		ethernet0 = &cp0_eth0;
+		ethernet1 = &cp0_eth1;
+		ethernet2 = &cp0_eth2;
+		ethernet3 = &cp1_eth0;
+		ethernet4 = &cp1_eth1;
+		ethernet5 = &cp1_eth2;
+		gpio1 = &cp0_gpio1;
+		gpio2 = &cp0_gpio2;
+		gpio3 = &cp1_gpio1;
+		gpio4 = &cp1_gpio2;
+	};
+
+	memory@00000000 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&cp0_uart0 {
+	status = "okay";
+};
+
+/* on-board eMMC - U9 */
+&ap_sdhci0 {
+	pinctrl-names = "default";
+	bus-width = <8>;
+	status = "okay";
+	mmc-ddr-1_8v;
+	mmc-hs400-1_8v;
+};
+
+&cp0_crypto {
+	status = "okay";
+};
+
+&cp0_xmdio {
+	status = "okay";
+	cp0_nbaset_phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <2>;
+	};
+	cp0_nbaset_phy1: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <0>;
+	};
+	cp0_nbaset_phy2: ethernet-phy@2 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <8>;
+	};
+};
+
+&cp0_ethernet {
+	status = "okay";
+};
+
+/* SLM-1521-V2, CON9 */
+&cp0_eth0 {
+	status = "okay";
+	phy-mode = "2500base-x";
+	phys = <&cp0_comphy2 0>;
+	managed = "in-band-status";
+};
+
+&cp0_eth1 {
+	status = "okay";
+	phy-mode = "2500base-x";
+	phys = <&cp0_comphy4 1>;
+	managed = "in-band-status";
+};
+
+&cp0_eth2 {
+	status = "okay";
+	phy-mode = "2500base-x";
+	phys = <&cp0_comphy5 2>;
+	managed = "in-band-status";
+};
+
+&cp0_gpio1 {
+	status = "okay";
+};
+
+&cp0_gpio2 {
+	status = "okay";
+};
+
+&cp0_i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_i2c0_pins>;
+	status = "okay";
+	clock-frequency = <100000>;
+	rtc@32 {
+		compatible = "epson,rx8130";
+		reg = <0x32>;
+		wakeup-source;
+	};
+};
+
+/* SLM-1521-V2, CON6 */
+&cp0_pcie0 {
+	status = "okay";
+	num-lanes = <2>;
+	num-viewport = <8>;
+	phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>;
+};
+
+/* U55 */
+&cp0_spi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_spi0_pins>;
+	reg = <0x700680 0x50>,          /* control */
+	      <0x2000000 0x1000000>;    /* CS0 */
+	status = "okay";
+	spi-flash@0 {
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		compatible = "jedec,spi-nor";
+		reg = <0x0>;
+		spi-max-frequency = <40000000>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			partition@0 {
+				label = "U-Boot";
+				reg = <0x0 0x1f0000>;
+			};
+			partition@1f0000 {
+				label = "U-Boot ENV Factory";
+				reg = <0x1f0000 0x10000>;
+			};
+			partition@200000 {
+				label = "Reserved";
+				reg = <0x200000 0x1f0000>;
+			};
+			partition@3f0000 {
+				label = "U-Boot ENV";
+				reg = <0x3f0000 0x10000>;
+			};
+		};
+	};
+};
+
+&cp0_syscon0 {
+	cp0_pinctrl: pinctrl {
+		compatible = "marvell,cp115-standalone-pinctrl";
+		cp0_i2c0_pins: cp0-i2c-pins-0 {
+			marvell,pins = "mpp37", "mpp38";
+			marvell,function = "i2c0";
+		};
+		cp0_i2c1_pins: cp0-i2c-pins-1 {
+			marvell,pins = "mpp35", "mpp36";
+			marvell,function = "i2c1";
+		};
+		cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
+			marvell,pins = "mpp0", "mpp1", "mpp2",
+				       "mpp3", "mpp4", "mpp5",
+				       "mpp6", "mpp7", "mpp8",
+				       "mpp9", "mpp10", "mpp11";
+			marvell,function = "ge0";
+		};
+		cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
+			marvell,pins = "mpp44", "mpp45", "mpp46",
+				       "mpp47", "mpp48", "mpp49",
+				       "mpp50", "mpp51", "mpp52",
+				       "mpp53", "mpp54", "mpp55";
+			marvell,function = "ge1";
+		};
+		cp0_spi0_pins: cp0-spi-pins-0 {
+			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
+			marvell,function = "spi1";
+		};
+	};
+};
+
+/*
+ * Instantiate the first connected CP115
+ */
+
+#define CP11X_NAME		cp1
+#define CP11X_BASE		f6000000
+#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
+#define CP11X_PCIE0_BASE	f6600000
+#define CP11X_PCIE1_BASE	f6620000
+#define CP11X_PCIE2_BASE	f6640000
+
+#include "armada-cp115.dtsi"
+
+#undef CP11X_NAME
+#undef CP11X_BASE
+#undef CP11X_PCIEx_MEM_BASE
+#undef CP11X_PCIEx_MEM_SIZE
+#undef CP11X_PCIE0_BASE
+#undef CP11X_PCIE1_BASE
+#undef CP11X_PCIE2_BASE
+
+&cp1_crypto {
+	status = "okay";
+};
+
+&cp1_xmdio {
+	status = "okay";
+	cp1_nbaset_phy0: ethernet-phy@3 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <2>;
+	};
+	cp1_nbaset_phy1: ethernet-phy@4 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <0>;
+	};
+	cp1_nbaset_phy2: ethernet-phy@5 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <8>;
+	};
+};
+
+&cp1_ethernet {
+	status = "okay";
+};
+
+/* CON50 */
+&cp1_eth0 {
+	status = "okay";
+	phy-mode = "2500base-x";
+	phys = <&cp1_comphy2 0>;
+	managed = "in-band-status";
+};
+
+&cp1_eth1 {
+	status = "okay";
+	phy-mode = "2500base-x";
+	phys = <&cp1_comphy4 1>;
+	managed = "in-band-status";
+};
+
+&cp1_eth2 {
+	status = "okay";
+	phy-mode = "2500base-x";
+	phys = <&cp1_comphy5 2>;
+	managed = "in-band-status";
+};
+
+&cp1_sata0 {
+	status = "okay";
+	sata-port@1 {
+		status = "okay";
+		phys = <&cp1_comphy0 1>;
+	};
+};
+
+&cp1_gpio1 {
+	status = "okay";
+};
+
+&cp1_gpio2 {
+	status = "okay";
+};
+
+&cp1_i2c0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp1_i2c0_pins>;
+	clock-frequency = <100000>;
+};
+
+&cp1_syscon0 {
+	cp1_pinctrl: pinctrl {
+		compatible = "marvell,cp115-standalone-pinctrl";
+		cp1_i2c0_pins: cp1-i2c-pins-0 {
+			marvell,pins = "mpp37", "mpp38";
+			marvell,function = "i2c0";
+		};
+		cp1_spi0_pins: cp1-spi-pins-0 {
+			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
+			marvell,function = "spi1";
+		};
+		cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
+			marvell,pins = "mpp3";
+			marvell,function = "gpio";
+		};
+		cp1_sfp_pins: sfp-pins {
+			marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
+			marvell,function = "gpio";
+		};
+	};
+};
+
+&cp1_usb3_1 {
+	status = "okay";
+	phys = <&cp1_comphy3 1>;
+	phy-names = "usb";
+};
diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts
new file mode 100644
index 0000000000..dc4e6527f1
--- /dev/null
+++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts
@@ -0,0 +1,481 @@ 
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * Device tree for the CN9132-DB board.
+ */
+
+#include "cn9130.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "iEi Puzzle-M902";
+	compatible = "iei,puzzle-m902",
+		     "marvell,armada-ap807-quad", "marvell,armada-ap807";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		i2c0 = &cp1_i2c0;
+		i2c1 = &cp0_i2c0;
+		gpio1 = &cp0_gpio1;
+		gpio2 = &cp0_gpio2;
+		gpio3 = &cp1_gpio1;
+		gpio4 = &cp1_gpio2;
+		gpio5 = &cp2_gpio1;
+		gpio6 = &cp2_gpio2;
+		ethernet0 = &cp0_eth0;
+		ethernet1 = &cp0_eth1;
+		ethernet2 = &cp0_eth2;
+		ethernet3 = &cp1_eth0;
+		ethernet4 = &cp1_eth1;
+		ethernet5 = &cp1_eth2;
+		ethernet6 = &cp2_eth0;
+		ethernet7 = &cp2_eth1;
+		ethernet8 = &cp2_eth2;
+		spi1 = &cp0_spi0;
+		spi2 = &cp0_spi1;
+		serial1 = &cp0_uart0;
+	};
+
+	memory@00000000 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+
+	cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
+		compatible = "regulator-fixed";
+		regulator-name = "cp2-xhci0-vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
+	};
+
+	cp2_usb3_0_phy0: cp2_usb3_phy0 {
+		compatible = "usb-nop-xceiv";
+		vcc-supply = <&cp2_reg_usb3_vbus0>;
+	};
+
+	cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
+		compatible = "regulator-fixed";
+		regulator-name = "cp2-xhci1-vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
+	};
+
+	cp2_usb3_0_phy1: cp2_usb3_phy1 {
+		compatible = "usb-nop-xceiv";
+		vcc-supply = <&cp2_reg_usb3_vbus1>;
+	};
+
+	cp2_sfp_eth0: sfp-eth0 {
+		compatible = "sff,sfp";
+		i2c-bus = <&cp2_sfpp0_i2c>;
+		los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
+		tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
+		status = "disabled";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&cp0_uart0 {
+	status = "okay";
+};
+
+/* on-board eMMC - U9 */
+&ap_sdhci0 {
+	pinctrl-names = "default";
+	bus-width = <8>;
+	status = "okay";
+	mmc-ddr-1_8v;
+	mmc-hs400-1_8v;
+};
+
+&cp0_crypto {
+	status = "okay";
+};
+
+&cp0_xmdio {
+	status = "okay";
+	cp0_nbaset_phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <2>;
+	};
+	cp0_nbaset_phy1: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <0>;
+	};
+	cp0_nbaset_phy2: ethernet-phy@2 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <8>;
+	};
+};
+
+&cp0_ethernet {
+	status = "okay";
+};
+
+/* SLM-1521-V2, CON9 */
+&cp0_eth0 {
+	status = "okay";
+	phy-mode = "10gbase-kr";
+	phys = <&cp0_comphy2 0>;
+	managed = "in-band-status";
+};
+
+&cp0_eth1 {
+	status = "okay";
+	phy-mode = "2500base-x";
+	phys = <&cp0_comphy4 1>;
+	managed = "in-band-status";
+};
+
+&cp0_eth2 {
+	status = "okay";
+	phy-mode = "2500base-x";
+	phys = <&cp0_comphy1 2>;
+	managed = "in-band-status";
+};
+
+&cp0_gpio1 {
+	status = "okay";
+};
+
+&cp0_gpio2 {
+	status = "okay";
+};
+
+&cp0_i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_i2c0_pins>;
+	status = "okay";
+	clock-frequency = <100000>;
+	rtc@32 {
+		compatible = "epson,rx8130";
+		reg = <0x32>;
+		wakeup-source;
+	};
+};
+
+&cp0_i2c1 {
+	clock-frequency = <100000>;
+};
+
+/* SLM-1521-V2, CON6 */
+&cp0_sata0 {
+	status = "okay";
+	sata-port@1 {
+		status = "okay";
+		phys = <&cp0_comphy0 1>;
+	};
+};
+
+&cp0_pcie2 {
+	status = "okay";
+	num-lanes = <1>;
+	num-viewport = <8>;
+	phys = <&cp0_comphy5 2>;
+};
+
+/* U55 */
+&cp0_spi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_spi0_pins>;
+	reg = <0x700680 0x50>,          /* control */
+	      <0x2000000 0x1000000>;    /* CS0 */
+	status = "okay";
+	spi-flash@0 {
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		compatible = "jedec,spi-nor";
+		reg = <0x0>;
+		spi-max-frequency = <40000000>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			partition@0 {
+				label = "U-Boot";
+				reg = <0x0 0x1f0000>;
+			};
+			partition@1f0000 {
+				label = "U-Boot ENV Factory";
+				reg = <0x1f0000 0x10000>;
+			};
+			partition@200000 {
+				label = "Reserved";
+				reg = <0x200000 0x1f0000>;
+			};
+			partition@3f0000 {
+				label = "U-Boot ENV";
+				reg = <0x3f0000 0x10000>;
+			};
+		};
+	};
+};
+
+&cp0_syscon0 {
+	cp0_pinctrl: pinctrl {
+		compatible = "marvell,cp115-standalone-pinctrl";
+		cp0_i2c0_pins: cp0-i2c-pins-0 {
+			marvell,pins = "mpp37", "mpp38";
+			marvell,function = "i2c0";
+		};
+		cp0_i2c1_pins: cp0-i2c-pins-1 {
+			marvell,pins = "mpp35", "mpp36";
+			marvell,function = "i2c1";
+		};
+		cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
+			marvell,pins = "mpp0", "mpp1", "mpp2",
+				       "mpp3", "mpp4", "mpp5",
+				       "mpp6", "mpp7", "mpp8",
+				       "mpp9", "mpp10", "mpp11";
+			marvell,function = "ge0";
+		};
+		cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
+			marvell,pins = "mpp44", "mpp45", "mpp46",
+				       "mpp47", "mpp48", "mpp49",
+				       "mpp50", "mpp51", "mpp52",
+				       "mpp53", "mpp54", "mpp55";
+			marvell,function = "ge1";
+		};
+		cp0_spi0_pins: cp0-spi-pins-0 {
+			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
+			marvell,function = "spi1";
+		};
+	};
+};
+
+&cp0_usb3_1 {
+	status = "okay";
+	phys = <&cp0_comphy3 1>;
+	phy-names = "usb";
+};
+
+/*
+ * Instantiate the first connected CP115
+ */
+
+#define CP11X_NAME		cp1
+#define CP11X_BASE		f4000000
+#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
+#define CP11X_PCIE0_BASE	f4600000
+#define CP11X_PCIE1_BASE	f4620000
+#define CP11X_PCIE2_BASE	f4640000
+
+#include "armada-cp115.dtsi"
+
+#undef CP11X_NAME
+#undef CP11X_BASE
+#undef CP11X_PCIEx_MEM_BASE
+#undef CP11X_PCIEx_MEM_SIZE
+#undef CP11X_PCIE0_BASE
+#undef CP11X_PCIE1_BASE
+#undef CP11X_PCIE2_BASE
+
+&cp1_crypto {
+	status = "okay";
+};
+
+&cp1_xmdio {
+	status = "okay";
+	cp1_nbaset_phy0: ethernet-phy@3 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <2>;
+	};
+	cp1_nbaset_phy1: ethernet-phy@4 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <0>;
+	};
+	cp1_nbaset_phy2: ethernet-phy@5 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <8>;
+	};
+};
+
+&cp1_ethernet {
+	status = "okay";
+};
+
+/* CON50 */
+&cp1_eth0 {
+	status = "okay";
+	phy-mode = "10gbase-kr";
+	phys = <&cp1_comphy2 0>;
+	managed = "in-band-status";
+};
+
+&cp1_eth1 {
+	status = "okay";
+	phy-mode = "2500base-x";
+	phys = <&cp1_comphy4 1>;
+	managed = "in-band-status";
+};
+
+&cp1_eth2 {
+	status = "okay";
+	phy-mode = "2500base-x";
+	phys = <&cp1_comphy1 2>;
+	managed = "in-band-status";
+};
+
+&cp1_gpio1 {
+	status = "okay";
+};
+
+&cp1_gpio2 {
+	status = "okay";
+};
+
+&cp1_i2c0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp1_i2c0_pins>;
+	clock-frequency = <100000>;
+};
+
+&cp1_syscon0 {
+	cp1_pinctrl: pinctrl {
+		compatible = "marvell,cp115-standalone-pinctrl";
+		cp1_i2c0_pins: cp1-i2c-pins-0 {
+			marvell,pins = "mpp37", "mpp38";
+			marvell,function = "i2c0";
+		};
+		cp1_spi0_pins: cp1-spi-pins-0 {
+			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
+			marvell,function = "spi1";
+		};
+		cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
+			marvell,pins = "mpp3";
+			marvell,function = "gpio";
+		};
+	};
+};
+
+/*
+ * Instantiate the second connected CP115
+ */
+
+#define CP11X_NAME		cp2
+#define CP11X_BASE		f6000000
+#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
+#define CP11X_PCIE0_BASE	f6600000
+#define CP11X_PCIE1_BASE	f6620000
+#define CP11X_PCIE2_BASE	f6640000
+
+#include "armada-cp115.dtsi"
+
+#undef CP11X_NAME
+#undef CP11X_BASE
+#undef CP11X_PCIEx_MEM_BASE
+#undef CP11X_PCIEx_MEM_SIZE
+#undef CP11X_PCIE0_BASE
+#undef CP11X_PCIE1_BASE
+#undef CP11X_PCIE2_BASE
+
+&cp2_crypto {
+	status = "okay";
+};
+
+&cp2_ethernet {
+	status = "okay";
+};
+
+&cp2_xmdio {
+	status = "okay";
+	cp2_nbaset_phy0: ethernet-phy@6 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <2>;
+	};
+	cp2_nbaset_phy1: ethernet-phy@7 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <0>;
+	};
+	cp2_nbaset_phy2: ethernet-phy@8 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <8>;
+	};
+};
+
+/* SLM-1521-V2, CON9 */
+&cp2_eth0 {
+	status = "okay";
+	phy-mode = "10gbase-kr";
+	phys = <&cp2_comphy2 0>;
+	managed = "in-band-status";
+};
+
+&cp2_eth1 {
+	status = "okay";
+	phy-mode = "2500base-x";
+	phys = <&cp2_comphy4 1>;
+	managed = "in-band-status";
+};
+
+&cp2_eth2 {
+	status = "okay";
+	phy-mode = "2500base-x";
+	phys = <&cp2_comphy1 2>;
+	managed = "in-band-status";
+};
+
+&cp2_gpio1 {
+	status = "okay";
+};
+
+&cp2_gpio2 {
+	status = "okay";
+};
+
+&cp2_i2c0 {
+	clock-frequency = <100000>;
+	/* SLM-1521-V2 - U3 */
+	i2c-mux@72 {
+		compatible = "nxp,pca9544";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x72>;
+		cp2_sfpp0_i2c: i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+		};
+
+		i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			/* U12 */
+			cp2_module_expander1: pca9555@21 {
+				compatible = "nxp,pca9555";
+				pinctrl-names = "default";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x21>;
+			};
+		};
+	};
+};
+
+&cp2_syscon0 {
+	cp2_pinctrl: pinctrl {
+		compatible = "marvell,cp115-standalone-pinctrl";
+		cp2_i2c0_pins: cp2-i2c-pins-0 {
+			marvell,pins = "mpp37", "mpp38";
+			marvell,function = "i2c0";
+		};
+	};
+};
diff --git a/target/linux/mvebu/image/cortexa72.mk b/target/linux/mvebu/image/cortexa72.mk
index 1440c07a0b..29727f8b9d 100644
--- a/target/linux/mvebu/image/cortexa72.mk
+++ b/target/linux/mvebu/image/cortexa72.mk
@@ -43,3 +43,21 @@  define Device/marvell_macchiatobin-singleshot
   SUPPORTED_DEVICES := marvell,armada8040-mcbin-singleshot
 endef
 TARGET_DEVICES += marvell_macchiatobin-singleshot
+
+define Device/iei_puzzle-m901
+  $(call Device/Default-arm64)
+  DEVICE_VENDOR := iEi
+  DEVICE_MODEL := Puzzle-M901
+  SOC := cn9131
+  IMAGE/sdcard.img.gz := boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata
+endef
+TARGET_DEVICES += iei_puzzle-m901
+
+define Device/iei_puzzle-m902
+  $(call Device/Default-arm64)
+  DEVICE_VENDOR := iEi
+  DEVICE_MODEL := Puzzle-M902
+  SOC := cn9132
+  IMAGE/sdcard.img.gz := boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata
+endef
+TARGET_DEVICES += iei_puzzle-m902