diff mbox series

[4/4] ath79: add support of Mikrotik RouterBoard 91xG series

Message ID 20210506162514.5913-5-denis281089@gmail.com
State Superseded
Delegated to: Koen Vandeputte
Headers show
Series RFC: ath79: add support for Mikrotik RB91xG | expand

Commit Message

Denis Kalashnikov May 6, 2021, 4:25 p.m. UTC
This board has been supported in the ar71xx.

Links:
* https://mikrotik.com/product/RB912UAG-2HPnD
* https://openwrt.org/toh/hwdata/mikrotik/mikrotik_rb912uag-2hpnd

Hardware:
 * SoC: Atheros AR9342, 1 core, 600MHz, MIPS, code name "Wasp"
   (like AR9341, AR9344, AR9350),

 * RAM: DDR 64MB,

 * Storage:
   * 64KB SPI NOR: chip Winbond 25X05. With Mikrotik first-stage Bootloader
     and hardware config (Ethernet MAC addr, wireless calibration data, etc).
     Driver: upstream m25p80/spi-nor.

   * 128MB NAND: chip Winbond W29N01GV. With Mikrotik second-stage Bootloader,
     kernel, initramfs, rootfs and user data. Driver: ad-hoc rb91x-nand,
     since Mikrotik guys doesn't use a SoC NAND controller on this board and
     controls NAND chip through gpio lines multiplexed with data lines by a
     latch,

 * Ethernet: x1 10/10/1000 port with POE, MAC is embedded in SoC and is
   managed by upstream ag71xx driver. PHY is on the separate chip AR8033,
   connected through RGMII and MDIO and controlled by upstream at803x driver,

 * Wi-Fi: 802.11bgn, MAC in SoC, driver: ath9k, wireless calibration data
   is in SPI NOR flash in hard_config partition (offset 0x1000),

 * PCIe: host controller embedded in SoC. Driver: ar724x. On PCIe there is
   only USB 2.0 ECHI host controller, connected to USB port and mPCIe slot,
   that can be used for LTE cell modem. Only one can be powerd at the same
   time.

 * SoC GPIO: 23 lines, driver: ath79-gpio,

 * SPI bus: SPI controller is embedded in SoC. 3 nCS lines. Devices:
   SPI NOR flash (nCS 0) and a Shift Register (see below, uses gpio line as
   nCS). Driver: ath79-spi.

 * Shift register: 8-bit, on SPI bus, chip 74HC595, driver: 74x164,
   nCS is on gpio line,

 * Latch: 8-bit latch, chip NXP LVC573A. Used for multiplaction of
   NAND control and data lines (NAND connected to SoC GPIO lines).
   Several lines of the latch, that is not used for NAND control lines,
   are used for power LED and user LED and nCS of a shift register,

 * Button: controlled by ???

 * Beeper/buzzer: controller by SoC gpio line ???

 * LEDs: 5 general purpose LEDs connected to the shift register,
   power LED and user LED, connected to the latch. All them can be
   controlled by software. Ethernet phy LED,

What is working:
 * Gigabit Ethernet (should be tested more under load),
 * SPI NOR and NAND flash (sysupgrade can be used),
 * 2.4 GHz Wi-Fi ('iw dev wlan0 scan' is working),
 * LEDs,

What is not working:
 * USB port and mPCIe slot,
 * Beeper,
 * Button,

You can flash image by sysupgrade utility or load it by net
(by DHCP/TFTP, hold the button while booting).

Signed-off-by: Denis Kalashnikov <denis281089@gmail.com>
---
 .../dts/ar9342_mikrotik_routerboard-912g.dts  | 314 ++++++++++++++++++
 target/linux/ath79/image/mikrotik.mk          |   9 +
 .../base-files/etc/board.d/02_network         |   2 +
 .../etc/hotplug.d/firmware/10-ath9k-eeprom    |   1 +
 .../base-files/lib/upgrade/platform.sh        |   1 +
 5 files changed, 327 insertions(+)
 create mode 100644 target/linux/ath79/dts/ar9342_mikrotik_routerboard-912g.dts

Comments

Koen Vandeputte May 7, 2021, 11:54 a.m. UTC | #1
On 06.05.21 18:25, Denis Kalashnikov wrote:

> What is not working:
>   * USB port and mPCIe slot,
>   * Beeper,
>   * Button,
>
> +
> +/* SoC Wi-Fi MAC managed by ath9k driver (RB912UAG-2HPnD) */
> +&wmac {
> +	status = "okay";
> +	/*
> +	 * Wireless calibration data is in SPI NOR flash
> +	 * hard_config partition. In OpenWrt you can also
> +	 * read it from sysfs file
> +	 * /sys/firmware/mikrotik/hard_config/wlan_data
> +	 * from offset 0x1000
> +	 * (/etc/hotplug.d/firmware/10-ath9k-eeprom script
> +	 * does this).
> +	 */
> +	qca,no-eeprom;
> +};

Add the following here in the dts to enable USB controller (tested and 
working)


&usb {
         status = "okay";
};

&usb_phy {
         status = "okay";
};
Koen Vandeputte May 7, 2021, 12:28 p.m. UTC | #2
On 06.05.21 18:25, Denis Kalashnikov wrote:
>
> What is not working:
>   * USB port and mPCIe slot,
>   * Beeper,
you will need to add kmod-gpio-beeper
> +/*
> + * TODO list:
> + *   - Enable beeper/buzzer,
> + *   - Enable button/key,
> + *   - Enable usb EHCI and export GPIOs for
> + *     turning on/off power for USB port and mPCIe slot,

fyi, The GPIO nr required for the USB target (USB type A or mini pcie 
slot) control is 61


> + *   - Test Wi-Fi working,
> + *   - Test Gigabit Ethernet working (see pll settings),
> + */
> +
> +/ {
> +	compatible = "mikrotik,routerboard-912g";
> +	model = "Mikrotik RB912G";
> +};
> +
> +&ahb {
> +	/*
> +	 * MFD: NAND plus GPIO-controller. They use/share SoC GPIO lines. Some of the
> +	 * GPIO lines are multiplexed by a 8-bit latch (LVC573).
> +	 * NAND is controlled by GPIO lines (bitbang), also some NAND control lines
> +	 * (nCE, ALE, CLE, READ) and data lines are multiplexed by a latch. So driver
> +	 * set control lines, enable latch ("latched them") and then transfer data.
> +	 * Several lines of the latch (not used for NAND control lines) are used
> +	 * as general-purpose GPIO. NAND ECC format is Mikrotik specific.
> +	 */
> +	/*
> +                                                                            +-----------+
> +                                                                            |           |
> ++-----------------+                                                         |           |
> +|                 |                                                         |           |
> +|                 |                                                         |           |
> +|                 |                                                         |           |   3-4 lines
> +|                 |                                                         |           +--------
> +|               G |                           8 lines                       |   8-bit   |    GPIO
> +|               P +-------+-------------------------------------------------+           |  (leds, SSR nCS)
> +|               I |       |                                                 |   Latch   |
> +|               O |       |                                                 |           |
> +|               s |       |                                                 |   LVC573  |  4 lines
> +|                 |       |                                                 |           +-------+
> +|                 |       |                                                 |           |       |
> +|                 |       |                                                 |           |       |
> +|                 |       |                                                 |           |       |
> +|                 |       |                                                 |           |       |
> +|                 |       |                                                 |           |       |
> +|                 |       | 8                                               +-----------+       |
> +|                 |       |                                                                     |
> +|                 |       | l                                                                   |
> +|                 |       | i                                                                   |
> +|      SoC        |       | n                                                                   |
> +|                 |       | e                                                                   |
> +|                 |       | s               +----------------------------------+                |
> +|                 |       |                 |                                  |                |
> +|                 |       |                 |                               C  |                |
> +|                 |       |                 |                                  | nCE, CLE, ALE, |
> +|                 |       |                 |                               O  +----------------+
> +|                 |       |                 | D                                |   READ
> +|                 |       |                 |                               N  |
> +|                 |       |                 | A                                |
> +|                 |       |                 |          N  A  N  D           T  |
> +|                 |       +-----------------+ T                                |
> +|                 |                         |                               R  | nRW, RDY
> +|                 |                         | A                                +----------+
> +|                 |                         |                               O  |          |
> +|                 |                         |                                  |          |
> +|                 |                         |                               L  |          |
> +|                 |                         |                                  |          |
> +|               G |                         |                                  |          |
> +|               P |                         +----------------------------------+          |
> +|               I |     2 lines                                                           |
> +|               O +-----------------------------------------------------------------------+
> +|               s |
> +|                 |
> ++-----------------+
> +	  Drawn on https://asciiflow.com
> +	*/

While it's nice info, please drop this drawing from the dts


> +	nand_gpio {
> +		compatible = "mikrotik,nand-gpio-latch";
> +
> +		/* NAND control gpios */
> +		nand-read-gpios = <&gpio 3 0>; /* Read */
> +		nand-rdy-gpios  = <&gpio 4 0>; /* Ready */
> +		nand-nrw-gpios  = <&gpio 12 GPIO_ACTIVE_LOW>; /* Read/Write Strobe */
> +		nand-nce-gpios  = <&gpio 13 GPIO_ACTIVE_LOW>; /* Chip Enable */
> +		nand-cle-gpios  = <&gpio 14 0>; /* Command Latch */
> +		nand-ale-gpios  = <&gpio 15 0>; /* Address Latch */
> +
> +		/* Latch Enable */
> +		nle-gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
> +
> +		nand-data-gpios = <&gpio 0 0>,
> +				  <&gpio 1 0>,
> +				  <&gpio 2 0>,
> +				  <&gpio 3 0>,
> +				  <&gpio 4 0>,
> +				  <&gpio 13 0>,
> +				  <&gpio 14 0>,
> +				  <&gpio 15 0>;
> +
> +		latch-gpios = <&gpio 0 GPIO_ACTIVE_LOW>,
> +			      <&gpio 1 GPIO_ACTIVE_LOW>,
> +			      <&gpio 2 GPIO_ACTIVE_LOW>;
> +
> +		nand {
> +			compatible = "mikrotik,rb91x-nand";
> +
> +			partitions {
> +				compatible = "fixed-partitions";
> +				#size-cells = <1>;
> +
> +				/* Mikrotik second-stage bootloader */
> +				partition@0 {
> +					label = "booter";
> +					reg = <0x0000000 0x0040000>;
> +					read-only;
> +				};
> +
> +				/* Kernel and initramfs */
> +				partition@40000 {
> +					label = "kernel";
> +					reg = <0x0040000 0x03c0000>;
> +				};
> +
> +				/* Read-only rootfs and user data (overlayfs) */
> +				partition@400000 {
> +					label = "ubi";
> +					reg = <0x0400000 0x7c00000>;
> +				};
> +			};
> +		};
Please drop the comments above from each partition.  The label itself is 
informative enough.
> +
> +		/*
> +		 * GPIO lines of the latch, that are not used for the NAND
> +		 * control lines. Used for Serial Shift register nCS and
> +		 * controling two LEDs: power adn user.
> +		 */
> +		gpio_latch: gpio {
> +			compatible = "mikrotik,rb91x-gpio-latch";
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +		};
> +	};
> +};
> +




Regarding this part:

> +/* We just copy-past this */
> +&mdio0 {
> +	status = "okay";
> +
> +	phy-mask = <0>;

> +
> +	phy0: ethernet-phy@0 {
> +		reg = <0>;
> +	};
> +};
> +
> +/* We just copy-paste this */
> +&eth0 {
> +	status = "okay";
> +
> +	/* pll-data = <0x02000000 0x00000101 0x00001313>; */
> +
> +	/* mtd-mac-address = <&hard_config 0x10>; */
> +
> +	phy-mode = "rgmii-id";
> +	phy-handle = <&phy0>;
> +
> +	gmac-config {
> +		device = <&gmac>;
> +		rxd-delay = <3>;
> +		rxdv-delay = <3>;
> +	};
> +};
> +

Here is the info from my old 912 addition patch which:

- also enables UART
- The gmac delays required are 1  iso  3


&uart {
        status = "okay";
};

&mdio0 {
         status = "okay";

         phy0: ethernet-phy@0 {
                 reg = <0>;
         };
};

&eth0 {
         status = "okay";

         phy-mode = "rgmii-id";
         phy-handle = <&phy0>;
         pll-data = <0x02000000 0xa0000101 0xa0001313>;

         gmac-config {
                 device = <&gmac>;
                 rgmii-gmac0 = <1>;
                 rgmii-enabled = <1>;
                 rxd-delay = <1>;
                 txd-delay = <1>;
         };
};

&wmac {
        status = "okay";

        qca,no-eeprom;
};



> +&spi {
> +	status = "okay";
> +
> +	/*
> +	 * New spi-ar934x driver (that superseeds spi-ath79 and support
> +	 * new shift-register mode) seems doesn't support gpio line nCS
> +	 * (cs-gpios) (do it?).
> +	 */
> +	compatible = "qca,ar7100-spi";
> +
> +	/* Gpio nCS line for the shift register */
> +	cs-gpios = <0>, <&gpio_latch 0 GPIO_ACTIVE_LOW>;
> +
> +	/* 64KB NOR SPI flash with routerboot and board config data */
> +	flash@0 {
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;
> +		spi-max-frequency = <25000000>;
> +
> +		partitions {
> +			compatible = "mikrotik,routerboot-partitions";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			/* Mikrotik first-stage Bootloader */
> +			partition@0 {
> +				label = "routerboot";
> +				reg = <0x0 0x0>;
> +				read-only;
> +			};
> +
> +			/*
> +			 * Ethernet MAC address, wireless calibration data,
> +			 * etc. You can read them from
> +			 * /sys/firmware/mikrotik/hard_config.
> +			 * You don't need to use rbcfg util anymore.
> +			 */
> +			hard_config: hard_config {
> +				read-only;
> +			};
> +
> +			bios {
> +				size = <0x1000>;
> +				read-only;
> +			};
> +
> +			/* Mikrotik Bootloader's Config */
> +			soft_config {
> +			};
> +		};
> +	};
> +
> +	/*
> +	 * 8-bit Shift register 74HC595 used as output GPIO chip (5 LEDs and
> +	 * 2 lines for turning on/off power for USB port and mPCIe slot).
> +	 * nCS is connected to gpio line (not to the internal SPI controller
> +	 * line), this line goes from the SoC through the latch.
> +	 */
> +	ssr: ssr@1 {
> +		compatible = "fairchild,74hc595";
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		registers-number = <1>;
> +		/* SPI params */
> +		reg = <1>;
> +		spi-max-frequency = <10000000>;

The chip used on the board is correct, and the datasheet mentions a 
speed of 50MHz


> +	};
> +};
> +
> +/ {
> +	leds {
> +		compatible = "gpio-leds";
> +
> +		led_power {
> +			label = "green:power";
> +			gpios = <&gpio_latch 1 GPIO_ACTIVE_HIGH>;
> +			default-state = "on";
> +		};
> +
> +		led_user {
> +			label = "green:user";
> +			gpios = <&gpio_latch 2 GPIO_ACTIVE_HIGH>;
> +		};
> +
> +		led1 {
> +			label = "green:led1";
> +			gpios = <&ssr 0 GPIO_ACTIVE_HIGH>;
> +		};
> +
> +		led2 {
> +			label = "green:led2";
> +			gpios = <&ssr 1 GPIO_ACTIVE_HIGH>;
> +		};
> +
> +		led3 {
> +			label = "green:led3";
> +			gpios = <&ssr 2 GPIO_ACTIVE_HIGH>;
> +		};
> +
> +		led4 {
> +			label = "green:led4";
> +			gpios = <&ssr 3 GPIO_ACTIVE_HIGH>;
> +		};
> +
> +		led5 {
> +			label = "green:led5";
> +			gpios = <&ssr 4 GPIO_ACTIVE_HIGH>;
> +			default-state = "on";
> +		};
> +	};
> +
> +	/* Is not working now -- we don't know why */
> +	beeper {
> +		compatible = "gpio-beeper";
> +		gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
> +	};
> +};
> +
> +/* It is needed for USB port and mPCIe slot */
> +&pcie {
> +	status = "okay";
> +};
> +
> +/* SoC Wi-Fi MAC managed by ath9k driver (RB912UAG-2HPnD) */
> +&wmac {
> +	status = "okay";
> +	/*
> +	 * Wireless calibration data is in SPI NOR flash
> +	 * hard_config partition. In OpenWrt you can also
> +	 * read it from sysfs file
> +	 * /sys/firmware/mikrotik/hard_config/wlan_data
> +	 * from offset 0x1000
> +	 * (/etc/hotplug.d/firmware/10-ath9k-eeprom script
> +	 * does this).
> +	 */
> +	qca,no-eeprom;
> +};
> diff --git a/target/linux/ath79/image/mikrotik.mk b/target/linux/ath79/image/mikrotik.mk
> index 74f8603b5a..b9c21dab7d 100644
> --- a/target/linux/ath79/image/mikrotik.mk
> +++ b/target/linux/ath79/image/mikrotik.mk
> @@ -1,5 +1,14 @@
>   include ./common-mikrotik.mk
>   
> +define Device/mikrotik_routerboard-912g
> +  $(Device/mikrotik_nand)
> +  SOC := ar9342
> +  DEVICE_MODEL := RouterBOARD 912G
> +  DEVICE_PACKAGES += kmod-usb-ehci kmod-usb2

add  kmod-gpio-beeper


I'll test some more later on.

Regards,

Koen
Adrian Schmutzler May 8, 2021, 7:05 p.m. UTC | #3
Hi,

nitpick, but if this is only for 912G, it should also say that in the commit title.

Other comments below.

>  .../dts/ar9342_mikrotik_routerboard-912g.dts  | 314 ++++++++++++++++++
>  target/linux/ath79/image/mikrotik.mk          |   9 +
>  .../base-files/etc/board.d/02_network         |   2 +
>  .../etc/hotplug.d/firmware/10-ath9k-eeprom    |   1 +
>  .../base-files/lib/upgrade/platform.sh        |   1 +
>  5 files changed, 327 insertions(+)
>  create mode 100644 target/linux/ath79/dts/ar9342_mikrotik_routerboard-
> 912g.dts
> 
> diff --git a/target/linux/ath79/dts/ar9342_mikrotik_routerboard-912g.dts
> b/target/linux/ath79/dts/ar9342_mikrotik_routerboard-912g.dts
> new file mode 100644
> index 0000000000..bc4aeeb6d0
> --- /dev/null
> +++ b/target/linux/ath79/dts/ar9342_mikrotik_routerboard-912g.dts
> @@ -0,0 +1,314 @@
> +#include "ar9344.dtsi"

Please add an SPDX license header.

> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +
> +/*
> + * TODO list:
> + *   - Enable beeper/buzzer,
> + *   - Enable button/key,
> + *   - Enable usb EHCI and export GPIOs for
> + *     turning on/off power for USB port and mPCIe slot,
> + *   - Test Wi-Fi working,
> + *   - Test Gigabit Ethernet working (see pll settings),
> + */
> +
> +/ {
> +	compatible = "mikrotik,routerboard-912g";
> +	model = "Mikrotik RB912G";

Please be consistent and also call it "Mikrotik RouterBOARD 912G" here.

> +};
> +
> +&ahb {
> +	/*
> +	 * MFD: NAND plus GPIO-controller. They use/share SoC GPIO lines.
> Some of the
> +	 * GPIO lines are multiplexed by a 8-bit latch (LVC573).
> +	 * NAND is controlled by GPIO lines (bitbang), also some NAND
> control lines
> +	 * (nCE, ALE, CLE, READ) and data lines are multiplexed by a latch. So
> driver
> +	 * set control lines, enable latch ("latched them") and then transfer
> data.
> +	 * Several lines of the latch (not used for NAND control lines) are
> used
> +	 * as general-purpose GPIO. NAND ECC format is Mikrotik specific.
> +	 */
> +	/*
> +                                                                            +-----------+
> +                                                                            |           |
> ++-----------------+                                                         |           |
> +|                 |                                                         |           |
> +|                 |                                                         |           |
> +|                 |                                                         |           |   3-4 lines
> +|                 |                                                         |           +--------
> +|               G |                           8 lines                       |   8-bit   |    GPIO
> +|               P +-------+-------------------------------------------------+           |  (leds,
> SSR nCS)
> +|               I |       |                                                 |   Latch   |
> +|               O |       |                                                 |           |
> +|               s |       |                                                 |   LVC573  |  4 lines
> +|                 |       |                                                 |           +-------+
> +|                 |       |                                                 |           |       |
> +|                 |       |                                                 |           |       |
> +|                 |       |                                                 |           |       |
> +|                 |       |                                                 |           |       |
> +|                 |       |                                                 |           |       |
> +|                 |       | 8                                               +-----------+       |
> +|                 |       |                                                                     |
> +|                 |       | l                                                                   |
> +|                 |       | i                                                                   |
> +|      SoC        |       | n                                                                   |
> +|                 |       | e                                                                   |
> +|                 |       | s               +----------------------------------+                |
> +|                 |       |                 |                                  |                |
> +|                 |       |                 |                               C  |                |
> +|                 |       |                 |                                  | nCE, CLE, ALE, |
> +|                 |       |                 |                               O  +----------------+
> +|                 |       |                 | D                                |   READ
> +|                 |       |                 |                               N  |
> +|                 |       |                 | A                                |
> +|                 |       |                 |          N  A  N  D           T  |
> +|                 |       +-----------------+ T                                |
> +|                 |                         |                               R  | nRW, RDY
> +|                 |                         | A                                +----------+
> +|                 |                         |                               O  |          |
> +|                 |                         |                                  |          |
> +|                 |                         |                               L  |          |
> +|                 |                         |                                  |          |
> +|               G |                         |                                  |          |
> +|               P |                         +----------------------------------+          |
> +|               I |     2 lines                                                           |
> +|               O +-----------------------------------------------------------------------+
> +|               s |
> +|                 |
> ++-----------------+
> +	  Drawn on https://asciiflow.com
> +	*/

This "drawing" should be removed here. This should be put either in the Wiki or in the commit message, if you need to preserve it close to the code.

> +	nand_gpio {
> +		compatible = "mikrotik,nand-gpio-latch";
> +
> +		/* NAND control gpios */
> +		nand-read-gpios = <&gpio 3 0>; /* Read */
> +		nand-rdy-gpios  = <&gpio 4 0>; /* Ready */
> +		nand-nrw-gpios  = <&gpio 12 GPIO_ACTIVE_LOW>; /*
> Read/Write Strobe */
> +		nand-nce-gpios  = <&gpio 13 GPIO_ACTIVE_LOW>; /* Chip
> Enable */
> +		nand-cle-gpios  = <&gpio 14 0>; /* Command Latch */
> +		nand-ale-gpios  = <&gpio 15 0>; /* Address Latch */

Any reason for this mixture of macro and plain numbers?

> +
> +		/* Latch Enable */
> +		nle-gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
> +
> +		nand-data-gpios = <&gpio 0 0>,
> +				  <&gpio 1 0>,
> +				  <&gpio 2 0>,
> +				  <&gpio 3 0>,
> +				  <&gpio 4 0>,
> +				  <&gpio 13 0>,
> +				  <&gpio 14 0>,
> +				  <&gpio 15 0>;
> +
> +		latch-gpios = <&gpio 0 GPIO_ACTIVE_LOW>,
> +			      <&gpio 1 GPIO_ACTIVE_LOW>,
> +			      <&gpio 2 GPIO_ACTIVE_LOW>;
> +
> +		nand {
> +			compatible = "mikrotik,rb91x-nand";
> +
> +			partitions {
> +				compatible = "fixed-partitions";
> +				#size-cells = <1>;
> +
> +				/* Mikrotik second-stage bootloader */
> +				partition@0 {
> +					label = "booter";
> +					reg = <0x0000000 0x0040000>;

0x0 should be fine here for the reg offset.

> +					read-only;
> +				};
> +
> +				/* Kernel and initramfs */
> +				partition@40000 {
> +					label = "kernel";
> +					reg = <0x0040000 0x03c0000>;
> +				};
> +
> +				/* Read-only rootfs and user data (overlayfs)
> */
> +				partition@400000 {
> +					label = "ubi";
> +					reg = <0x0400000 0x7c00000>;
> +				};
> +			};
> +		};
> +
> +		/*
> +		 * GPIO lines of the latch, that are not used for the NAND
> +		 * control lines. Used for Serial Shift register nCS and
> +		 * controling two LEDs: power adn user.
> +		 */
> +		gpio_latch: gpio {
> +			compatible = "mikrotik,rb91x-gpio-latch";
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +		};
> +	};
> +};
> +
> +/* We just copy-past this */

What's that supposed to tell?

> +&mdio0 {
> +	status = "okay";
> +
> +	phy-mask = <0>;
> +
> +	phy0: ethernet-phy@0 {
> +		reg = <0>;
> +	};
> +};
> +
> +/* We just copy-paste this */
> +&eth0 {
> +	status = "okay";
> +
> +	/* pll-data = <0x02000000 0x00000101 0x00001313>; */
> +
> +	/* mtd-mac-address = <&hard_config 0x10>; */
> +
> +	phy-mode = "rgmii-id";
> +	phy-handle = <&phy0>;
> +
> +	gmac-config {
> +		device = <&gmac>;
> +		rxd-delay = <3>;
> +		rxdv-delay = <3>;
> +	};
> +};
> +
> +&spi {
> +	status = "okay";
> +
> +	/*
> +	 * New spi-ar934x driver (that superseeds spi-ath79 and support
> +	 * new shift-register mode) seems doesn't support gpio line nCS
> +	 * (cs-gpios) (do it?).
> +	 */
> +	compatible = "qca,ar7100-spi";
> +
> +	/* Gpio nCS line for the shift register */
> +	cs-gpios = <0>, <&gpio_latch 0 GPIO_ACTIVE_LOW>;
> +
> +	/* 64KB NOR SPI flash with routerboot and board config data */
> +	flash@0 {
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;
> +		spi-max-frequency = <25000000>;
> +
> +		partitions {
> +			compatible = "mikrotik,routerboot-partitions";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			/* Mikrotik first-stage Bootloader */
> +			partition@0 {
> +				label = "routerboot";
> +				reg = <0x0 0x0>;
> +				read-only;
> +			};
> +
> +			/*
> +			 * Ethernet MAC address, wireless calibration data,
> +			 * etc. You can read them from
> +			 * /sys/firmware/mikrotik/hard_config.
> +			 * You don't need to use rbcfg util anymore.
> +			 */
> +			hard_config: hard_config {
> +				read-only;
> +			};
> +
> +			bios {
> +				size = <0x1000>;
> +				read-only;
> +			};
> +
> +			/* Mikrotik Bootloader's Config */
> +			soft_config {
> +			};
> +		};
> +	};
> +
> +	/*
> +	 * 8-bit Shift register 74HC595 used as output GPIO chip (5 LEDs and
> +	 * 2 lines for turning on/off power for USB port and mPCIe slot).
> +	 * nCS is connected to gpio line (not to the internal SPI controller
> +	 * line), this line goes from the SoC through the latch.
> +	 */
> +	ssr: ssr@1 {
> +		compatible = "fairchild,74hc595";
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		registers-number = <1>;
> +		/* SPI params */
> +		reg = <1>;
> +		spi-max-frequency = <10000000>;
> +	};
> +};
> +
> +/ {
> +	leds {
> +		compatible = "gpio-leds";
> +
> +		led_power {
> +			label = "green:power";
> +			gpios = <&gpio_latch 1 GPIO_ACTIVE_HIGH>;
> +			default-state = "on";
> +		};
> +
> +		led_user {
> +			label = "green:user";
> +			gpios = <&gpio_latch 2 GPIO_ACTIVE_HIGH>;
> +		};
> +
> +		led1 {
> +			label = "green:led1";
> +			gpios = <&ssr 0 GPIO_ACTIVE_HIGH>;
> +		};
> +
> +		led2 {
> +			label = "green:led2";
> +			gpios = <&ssr 1 GPIO_ACTIVE_HIGH>;
> +		};
> +
> +		led3 {
> +			label = "green:led3";
> +			gpios = <&ssr 2 GPIO_ACTIVE_HIGH>;
> +		};
> +
> +		led4 {
> +			label = "green:led4";
> +			gpios = <&ssr 3 GPIO_ACTIVE_HIGH>;
> +		};
> +
> +		led5 {
> +			label = "green:led5";
> +			gpios = <&ssr 4 GPIO_ACTIVE_HIGH>;
> +			default-state = "on";

default-on by intention?

> +		};
> +	};
> +
> +	/* Is not working now -- we don't know why */
> +	beeper {
> +		compatible = "gpio-beeper";
> +		gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
> +	};
> +};
> +
> +/* It is needed for USB port and mPCIe slot */ &pcie {
> +	status = "okay";
> +};
> +
> +/* SoC Wi-Fi MAC managed by ath9k driver (RB912UAG-2HPnD) */ &wmac {
> +	status = "okay";
> +	/*
> +	 * Wireless calibration data is in SPI NOR flash
> +	 * hard_config partition. In OpenWrt you can also
> +	 * read it from sysfs file
> +	 * /sys/firmware/mikrotik/hard_config/wlan_data
> +	 * from offset 0x1000
> +	 * (/etc/hotplug.d/firmware/10-ath9k-eeprom script
> +	 * does this).
> +	 */
> +	qca,no-eeprom;
> +};
> diff --git a/target/linux/ath79/image/mikrotik.mk
> b/target/linux/ath79/image/mikrotik.mk
> index 74f8603b5a..b9c21dab7d 100644
> --- a/target/linux/ath79/image/mikrotik.mk
> +++ b/target/linux/ath79/image/mikrotik.mk
> @@ -1,5 +1,14 @@
>  include ./common-mikrotik.mk
> 
> +define Device/mikrotik_routerboard-912g

Please care about alphabetic sorting.

> +  $(Device/mikrotik_nand)
> +  SOC := ar9342
> +  DEVICE_MODEL := RouterBOARD 912G
> +  DEVICE_PACKAGES += kmod-usb-ehci kmod-usb2
> +  SUPPORTED_DEVICES += rb-912g

Have you checked that this is the correct string for ar71xx?

Best

> +endef
> +TARGET_DEVICES += mikrotik_routerboard-912g
> +
>  define Device/mikrotik_routerboard-493g
>    $(Device/mikrotik_nand)
>    SOC := ar7161
> diff --git a/target/linux/ath79/mikrotik/base-files/etc/board.d/02_network
> b/target/linux/ath79/mikrotik/base-files/etc/board.d/02_network
> index 4ffe82588c..07bb22c088 100644
> --- a/target/linux/ath79/mikrotik/base-files/etc/board.d/02_network
> +++ b/target/linux/ath79/mikrotik/base-files/etc/board.d/02_network
> @@ -14,6 +14,7 @@ ath79_setup_interfaces()
>  		ucidef_add_switch "switch1" \
>  			"0@eth1" "1:lan:4" "2:lan:1" "3:lan:2" "4:lan:3"
>  		;;
> +	mikrotik,routerboard-912g|\
>  	mikrotik,routerboard-921gs-5hpacd-15s|\
>  	mikrotik,routerboard-lhg-2nd|\
>  	mikrotik,routerboard-sxt-5nd-r2|\
> @@ -36,6 +37,7 @@ ath79_setup_macs()
>  	local mac_base="$(cat
> /sys/firmware/mikrotik/hard_config/mac_base)"
> 
>  	case "$board" in
> +	mikrotik,routerboard-912g|\
>  	mikrotik,routerboard-921gs-5hpacd-15s|\
>  	mikrotik,routerboard-lhg-2nd|\
>  	mikrotik,routerboard-sxt-5nd-r2|\
> diff --git a/target/linux/ath79/mikrotik/base-
> files/etc/hotplug.d/firmware/10-ath9k-eeprom
> b/target/linux/ath79/mikrotik/base-files/etc/hotplug.d/firmware/10-ath9k-
> eeprom
> index 7ef6fdbe0f..7868ceaac9 100644
> --- a/target/linux/ath79/mikrotik/base-files/etc/hotplug.d/firmware/10-
> ath9k-eeprom
> +++ b/target/linux/ath79/mikrotik/base-files/etc/hotplug.d/firmware/10-a
> +++ th9k-eeprom
> @@ -23,6 +23,7 @@ board=$(board_name)
>  case "$FIRMWARE" in
>  "ath9k-eeprom-ahb-18100000.wmac.bin")
>  	case $board in
> +	mikrotik,routerboard-912g|\
>  	mikrotik,routerboard-lhg-2nd|\
>  	mikrotik,routerboard-sxt-5nd-r2|\
>  	mikrotik,routerboard-wapr-2nd)
> diff --git a/target/linux/ath79/mikrotik/base-files/lib/upgrade/platform.sh
> b/target/linux/ath79/mikrotik/base-files/lib/upgrade/platform.sh
> index 97d388168f..736a0932f7 100644
> --- a/target/linux/ath79/mikrotik/base-files/lib/upgrade/platform.sh
> +++ b/target/linux/ath79/mikrotik/base-files/lib/upgrade/platform.sh
> @@ -32,6 +32,7 @@ platform_do_upgrade() {
> 
>  	case "$board" in
>  	mikrotik,routerboard-493g|\
> +	mikrotik,routerboard-912g|\
>  	mikrotik,routerboard-921gs-5hpacd-15s|\
>  	mikrotik,routerboard-922uags-5hpacd|\
>  	mikrotik,routerboard-sxt-5nd-r2)
> --
> 2.26.3
> 
> 
> _______________________________________________
> openwrt-devel mailing list
> openwrt-devel@lists.openwrt.org
> https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Sergey Ryazanov May 14, 2021, 3:04 a.m. UTC | #4
On Thu, May 6, 2021 at 7:32 PM Denis Kalashnikov <denis281089@gmail.com> wrote:
> +       /*
> +        * MFD: NAND plus GPIO-controller. They use/share SoC GPIO lines. Some of the
> +        * GPIO lines are multiplexed by a 8-bit latch (LVC573).
> +        * NAND is controlled by GPIO lines (bitbang), also some NAND control lines
> +        * (nCE, ALE, CLE, READ) and data lines are multiplexed by a latch. So driver
> +        * set control lines, enable latch ("latched them") and then transfer data.
> +        * Several lines of the latch (not used for NAND control lines) are used
> +        * as general-purpose GPIO. NAND ECC format is Mikrotik specific.
> +        */
> +       /*
> +                                                                            +-----------+
> +                                                                            |           |
> ++-----------------+                                                         |           |
> +|                 |                                                         |           |
> +|                 |                                                         |           |
> +|                 |                                                         |           |   3-4 lines
> +|                 |                                                         |           +--------
> +|               G |                           8 lines                       |   8-bit   |    GPIO
> +|               P +-------+-------------------------------------------------+           |  (leds, SSR nCS)
> +|               I |       |                                                 |   Latch   |
> +|               O |       |                                                 |           |
> +|               s |       |                                                 |   LVC573  |  4 lines
> +|                 |       |                                                 |           +-------+
> +|                 |       |                                                 |           |       |
> +|                 |       |                                                 |           |       |
> +|                 |       |                                                 |           |       |
> +|                 |       |                                                 |           |       |
> +|                 |       |                                                 |           |       |
> +|                 |       | 8                                               +-----------+       |
> +|                 |       |                                                                     |
> +|                 |       | l                                                                   |
> +|                 |       | i                                                                   |
> +|      SoC        |       | n                                                                   |
> +|                 |       | e                                                                   |
> +|                 |       | s               +----------------------------------+                |
> +|                 |       |                 |                                  |                |
> +|                 |       |                 |                               C  |                |
> +|                 |       |                 |                                  | nCE, CLE, ALE, |
> +|                 |       |                 |                               O  +----------------+
> +|                 |       |                 | D                                |   READ
> +|                 |       |                 |                               N  |
> +|                 |       |                 | A                                |
> +|                 |       |                 |          N  A  N  D           T  |
> +|                 |       +-----------------+ T                                |
> +|                 |                         |                               R  | nRW, RDY
> +|                 |                         | A                                +----------+
> +|                 |                         |                               O  |          |
> +|                 |                         |                                  |          |
> +|                 |                         |                               L  |          |
> +|                 |                         |                                  |          |
> +|               G |                         |                                  |          |
> +|               P |                         +----------------------------------+          |
> +|               I |     2 lines                                                           |
> +|               O +-----------------------------------------------------------------------+
> +|               s |
> +|                 |
> ++-----------------+

This drawing has a small drawback. Looks like NAND RDY has no
dedicated line and shares GPIO with the NAND Data#4.

> +       nand_gpio {
> +               compatible = "mikrotik,nand-gpio-latch";
> +
> +               /* NAND control gpios */
> +               nand-read-gpios = <&gpio 3 0>; /* Read */
> +               nand-rdy-gpios  = <&gpio 4 0>; /* Ready */
> +               nand-nrw-gpios  = <&gpio 12 GPIO_ACTIVE_LOW>; /* Read/Write Strobe */
> +               nand-nce-gpios  = <&gpio 13 GPIO_ACTIVE_LOW>; /* Chip Enable */
> +               nand-cle-gpios  = <&gpio 14 0>; /* Command Latch */
> +               nand-ale-gpios  = <&gpio 15 0>; /* Address Latch */
> +
> +               /* Latch Enable */
> +               nle-gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
> +
> +               nand-data-gpios = <&gpio 0 0>,
> +                                 <&gpio 1 0>,
> +                                 <&gpio 2 0>,
> +                                 <&gpio 3 0>,
> +                                 <&gpio 4 0>,
> +                                 <&gpio 13 0>,
> +                                 <&gpio 14 0>,
> +                                 <&gpio 15 0>;
> +
> +               latch-gpios = <&gpio 0 GPIO_ACTIVE_LOW>,
> +                             <&gpio 1 GPIO_ACTIVE_LOW>,
> +                             <&gpio 2 GPIO_ACTIVE_LOW>;

This driver is highly board specific and we use DTS not to configure
it, but mostly to document HW interconnections. Also it is unusual
when a same GPIO line is referenced multiple times from different
properties. So maybe we should use a single property with magic
positions and accomplish interconnection description with comments?
E.g.

        gpios = <&gpio 0 ...>,  /* NAND Data#0 / SSR strobe (SPI CS) */
                <&gpio 1 ...>,  /* NAND Data#1 / Power LED */
                <&gpio 2 ...>,  /* NAND Data#2 / User LED */
                <&gpio 3 ...>,  /* NAND Data#3 / NAND Read */
                <&gpio 4 ...>,  /* NAND Data#4 / NAND RDY */
                <&gpio 13 ...>, /* NAND Data#5 / NAND nCE */
                <&gpio 14 ...>, /* NAND Data#6 / NAND CLE */
                <&gpio 15 ...>, /* NAND Data#7 / NAND ALE */
                <&gpio 11 ...>; /* Latch enable */

This will simplify the driver code.

--
Sergey
diff mbox series

Patch

diff --git a/target/linux/ath79/dts/ar9342_mikrotik_routerboard-912g.dts b/target/linux/ath79/dts/ar9342_mikrotik_routerboard-912g.dts
new file mode 100644
index 0000000000..bc4aeeb6d0
--- /dev/null
+++ b/target/linux/ath79/dts/ar9342_mikrotik_routerboard-912g.dts
@@ -0,0 +1,314 @@ 
+#include "ar9344.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/*
+ * TODO list:
+ *   - Enable beeper/buzzer,
+ *   - Enable button/key,
+ *   - Enable usb EHCI and export GPIOs for
+ *     turning on/off power for USB port and mPCIe slot,
+ *   - Test Wi-Fi working,
+ *   - Test Gigabit Ethernet working (see pll settings),
+ */
+
+/ {
+	compatible = "mikrotik,routerboard-912g";
+	model = "Mikrotik RB912G";
+};
+
+&ahb {
+	/*
+	 * MFD: NAND plus GPIO-controller. They use/share SoC GPIO lines. Some of the
+	 * GPIO lines are multiplexed by a 8-bit latch (LVC573).
+	 * NAND is controlled by GPIO lines (bitbang), also some NAND control lines
+	 * (nCE, ALE, CLE, READ) and data lines are multiplexed by a latch. So driver
+	 * set control lines, enable latch ("latched them") and then transfer data.
+	 * Several lines of the latch (not used for NAND control lines) are used
+	 * as general-purpose GPIO. NAND ECC format is Mikrotik specific.
+	 */
+	/*
+                                                                            +-----------+
+                                                                            |           |
++-----------------+                                                         |           |
+|                 |                                                         |           |
+|                 |                                                         |           |
+|                 |                                                         |           |   3-4 lines
+|                 |                                                         |           +--------
+|               G |                           8 lines                       |   8-bit   |    GPIO
+|               P +-------+-------------------------------------------------+           |  (leds, SSR nCS)
+|               I |       |                                                 |   Latch   |
+|               O |       |                                                 |           |
+|               s |       |                                                 |   LVC573  |  4 lines
+|                 |       |                                                 |           +-------+
+|                 |       |                                                 |           |       |
+|                 |       |                                                 |           |       |
+|                 |       |                                                 |           |       |
+|                 |       |                                                 |           |       |
+|                 |       |                                                 |           |       |
+|                 |       | 8                                               +-----------+       |
+|                 |       |                                                                     |
+|                 |       | l                                                                   |
+|                 |       | i                                                                   |
+|      SoC        |       | n                                                                   |
+|                 |       | e                                                                   |
+|                 |       | s               +----------------------------------+                |
+|                 |       |                 |                                  |                |
+|                 |       |                 |                               C  |                |
+|                 |       |                 |                                  | nCE, CLE, ALE, |
+|                 |       |                 |                               O  +----------------+
+|                 |       |                 | D                                |   READ
+|                 |       |                 |                               N  |
+|                 |       |                 | A                                |
+|                 |       |                 |          N  A  N  D           T  |
+|                 |       +-----------------+ T                                |
+|                 |                         |                               R  | nRW, RDY
+|                 |                         | A                                +----------+
+|                 |                         |                               O  |          |
+|                 |                         |                                  |          |
+|                 |                         |                               L  |          |
+|                 |                         |                                  |          |
+|               G |                         |                                  |          |
+|               P |                         +----------------------------------+          |
+|               I |     2 lines                                                           |
+|               O +-----------------------------------------------------------------------+
+|               s |
+|                 |
++-----------------+
+	  Drawn on https://asciiflow.com
+	*/
+	nand_gpio {
+		compatible = "mikrotik,nand-gpio-latch";
+
+		/* NAND control gpios */
+		nand-read-gpios = <&gpio 3 0>; /* Read */
+		nand-rdy-gpios  = <&gpio 4 0>; /* Ready */
+		nand-nrw-gpios  = <&gpio 12 GPIO_ACTIVE_LOW>; /* Read/Write Strobe */
+		nand-nce-gpios  = <&gpio 13 GPIO_ACTIVE_LOW>; /* Chip Enable */
+		nand-cle-gpios  = <&gpio 14 0>; /* Command Latch */
+		nand-ale-gpios  = <&gpio 15 0>; /* Address Latch */
+
+		/* Latch Enable */
+		nle-gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+
+		nand-data-gpios = <&gpio 0 0>,
+				  <&gpio 1 0>,
+				  <&gpio 2 0>,
+				  <&gpio 3 0>,
+				  <&gpio 4 0>,
+				  <&gpio 13 0>,
+				  <&gpio 14 0>,
+				  <&gpio 15 0>;
+
+		latch-gpios = <&gpio 0 GPIO_ACTIVE_LOW>,
+			      <&gpio 1 GPIO_ACTIVE_LOW>,
+			      <&gpio 2 GPIO_ACTIVE_LOW>;
+
+		nand {
+			compatible = "mikrotik,rb91x-nand";
+
+			partitions {
+				compatible = "fixed-partitions";
+				#size-cells = <1>;
+
+				/* Mikrotik second-stage bootloader */
+				partition@0 {
+					label = "booter";
+					reg = <0x0000000 0x0040000>;
+					read-only;
+				};
+
+				/* Kernel and initramfs */
+				partition@40000 {
+					label = "kernel";
+					reg = <0x0040000 0x03c0000>;
+				};
+
+				/* Read-only rootfs and user data (overlayfs) */
+				partition@400000 {
+					label = "ubi";
+					reg = <0x0400000 0x7c00000>;
+				};
+			};
+		};
+
+		/*
+		 * GPIO lines of the latch, that are not used for the NAND
+		 * control lines. Used for Serial Shift register nCS and
+		 * controling two LEDs: power adn user.
+		 */
+		gpio_latch: gpio {
+			compatible = "mikrotik,rb91x-gpio-latch";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+	};
+};
+
+/* We just copy-past this */
+&mdio0 {
+	status = "okay";
+
+	phy-mask = <0>;
+
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+	};
+};
+
+/* We just copy-paste this */
+&eth0 {
+	status = "okay";
+
+	/* pll-data = <0x02000000 0x00000101 0x00001313>; */
+
+	/* mtd-mac-address = <&hard_config 0x10>; */
+
+	phy-mode = "rgmii-id";
+	phy-handle = <&phy0>;
+
+	gmac-config {
+		device = <&gmac>;
+		rxd-delay = <3>;
+		rxdv-delay = <3>;
+	};
+};
+
+&spi {
+	status = "okay";
+
+	/*
+	 * New spi-ar934x driver (that superseeds spi-ath79 and support
+	 * new shift-register mode) seems doesn't support gpio line nCS
+	 * (cs-gpios) (do it?).
+	 */
+	compatible = "qca,ar7100-spi";
+
+	/* Gpio nCS line for the shift register */
+	cs-gpios = <0>, <&gpio_latch 0 GPIO_ACTIVE_LOW>;
+
+	/* 64KB NOR SPI flash with routerboot and board config data */
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <25000000>;
+
+		partitions {
+			compatible = "mikrotik,routerboot-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			/* Mikrotik first-stage Bootloader */
+			partition@0 {
+				label = "routerboot";
+				reg = <0x0 0x0>;
+				read-only;
+			};
+
+			/*
+			 * Ethernet MAC address, wireless calibration data,
+			 * etc. You can read them from
+			 * /sys/firmware/mikrotik/hard_config.
+			 * You don't need to use rbcfg util anymore. 
+			 */
+			hard_config: hard_config {
+				read-only;
+			};
+
+			bios {
+				size = <0x1000>;
+				read-only;
+			};
+
+			/* Mikrotik Bootloader's Config */
+			soft_config {
+			};
+		};
+	};
+
+	/*
+	 * 8-bit Shift register 74HC595 used as output GPIO chip (5 LEDs and
+	 * 2 lines for turning on/off power for USB port and mPCIe slot).
+	 * nCS is connected to gpio line (not to the internal SPI controller
+	 * line), this line goes from the SoC through the latch.
+	 */
+	ssr: ssr@1 {
+		compatible = "fairchild,74hc595";
+		gpio-controller;
+		#gpio-cells = <2>;
+		registers-number = <1>;
+		/* SPI params */
+		reg = <1>;
+		spi-max-frequency = <10000000>;
+	};
+};
+
+/ {
+	leds {
+		compatible = "gpio-leds";
+
+		led_power {
+			label = "green:power";
+			gpios = <&gpio_latch 1 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		led_user {
+			label = "green:user";
+			gpios = <&gpio_latch 2 GPIO_ACTIVE_HIGH>;
+		};
+
+		led1 {
+			label = "green:led1";
+			gpios = <&ssr 0 GPIO_ACTIVE_HIGH>;
+		};
+
+		led2 {
+			label = "green:led2";
+			gpios = <&ssr 1 GPIO_ACTIVE_HIGH>;
+		};
+
+		led3 {
+			label = "green:led3";
+			gpios = <&ssr 2 GPIO_ACTIVE_HIGH>;
+		};
+
+		led4 {
+			label = "green:led4";
+			gpios = <&ssr 3 GPIO_ACTIVE_HIGH>;
+		};
+
+		led5 {
+			label = "green:led5";
+			gpios = <&ssr 4 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+	};
+
+	/* Is not working now -- we don't know why */
+	beeper {
+		compatible = "gpio-beeper";
+		gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+/* It is needed for USB port and mPCIe slot */
+&pcie {
+	status = "okay";
+};
+
+/* SoC Wi-Fi MAC managed by ath9k driver (RB912UAG-2HPnD) */
+&wmac {
+	status = "okay";
+	/*
+	 * Wireless calibration data is in SPI NOR flash
+	 * hard_config partition. In OpenWrt you can also
+	 * read it from sysfs file
+	 * /sys/firmware/mikrotik/hard_config/wlan_data
+	 * from offset 0x1000
+	 * (/etc/hotplug.d/firmware/10-ath9k-eeprom script
+	 * does this).
+	 */
+	qca,no-eeprom;
+};
diff --git a/target/linux/ath79/image/mikrotik.mk b/target/linux/ath79/image/mikrotik.mk
index 74f8603b5a..b9c21dab7d 100644
--- a/target/linux/ath79/image/mikrotik.mk
+++ b/target/linux/ath79/image/mikrotik.mk
@@ -1,5 +1,14 @@ 
 include ./common-mikrotik.mk
 
+define Device/mikrotik_routerboard-912g
+  $(Device/mikrotik_nand)
+  SOC := ar9342
+  DEVICE_MODEL := RouterBOARD 912G
+  DEVICE_PACKAGES += kmod-usb-ehci kmod-usb2
+  SUPPORTED_DEVICES += rb-912g
+endef
+TARGET_DEVICES += mikrotik_routerboard-912g
+
 define Device/mikrotik_routerboard-493g
   $(Device/mikrotik_nand)
   SOC := ar7161
diff --git a/target/linux/ath79/mikrotik/base-files/etc/board.d/02_network b/target/linux/ath79/mikrotik/base-files/etc/board.d/02_network
index 4ffe82588c..07bb22c088 100644
--- a/target/linux/ath79/mikrotik/base-files/etc/board.d/02_network
+++ b/target/linux/ath79/mikrotik/base-files/etc/board.d/02_network
@@ -14,6 +14,7 @@  ath79_setup_interfaces()
 		ucidef_add_switch "switch1" \
 			"0@eth1" "1:lan:4" "2:lan:1" "3:lan:2" "4:lan:3"
 		;;
+	mikrotik,routerboard-912g|\
 	mikrotik,routerboard-921gs-5hpacd-15s|\
 	mikrotik,routerboard-lhg-2nd|\
 	mikrotik,routerboard-sxt-5nd-r2|\
@@ -36,6 +37,7 @@  ath79_setup_macs()
 	local mac_base="$(cat /sys/firmware/mikrotik/hard_config/mac_base)"
 
 	case "$board" in
+	mikrotik,routerboard-912g|\
 	mikrotik,routerboard-921gs-5hpacd-15s|\
 	mikrotik,routerboard-lhg-2nd|\
 	mikrotik,routerboard-sxt-5nd-r2|\
diff --git a/target/linux/ath79/mikrotik/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom b/target/linux/ath79/mikrotik/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom
index 7ef6fdbe0f..7868ceaac9 100644
--- a/target/linux/ath79/mikrotik/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom
+++ b/target/linux/ath79/mikrotik/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom
@@ -23,6 +23,7 @@  board=$(board_name)
 case "$FIRMWARE" in
 "ath9k-eeprom-ahb-18100000.wmac.bin")
 	case $board in
+	mikrotik,routerboard-912g|\
 	mikrotik,routerboard-lhg-2nd|\
 	mikrotik,routerboard-sxt-5nd-r2|\
 	mikrotik,routerboard-wapr-2nd)
diff --git a/target/linux/ath79/mikrotik/base-files/lib/upgrade/platform.sh b/target/linux/ath79/mikrotik/base-files/lib/upgrade/platform.sh
index 97d388168f..736a0932f7 100644
--- a/target/linux/ath79/mikrotik/base-files/lib/upgrade/platform.sh
+++ b/target/linux/ath79/mikrotik/base-files/lib/upgrade/platform.sh
@@ -32,6 +32,7 @@  platform_do_upgrade() {
 
 	case "$board" in
 	mikrotik,routerboard-493g|\
+	mikrotik,routerboard-912g|\
 	mikrotik,routerboard-921gs-5hpacd-15s|\
 	mikrotik,routerboard-922uags-5hpacd|\
 	mikrotik,routerboard-sxt-5nd-r2)