diff mbox series

valgrind: Fix compile problem with MIPS soft float

Message ID 20210411094828.3925793-1-hauke@hauke-m.de
State Accepted
Delegated to: Hauke Mehrtens
Headers show
Series valgrind: Fix compile problem with MIPS soft float | expand

Commit Message

Hauke Mehrtens April 11, 2021, 9:48 a.m. UTC 
valgrind does not compile any more when using a GCC 10 for MIPS with
soft float. Just remove the parts which are generating assembler which
would not work.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
 .../patches/130-mips_fix_soft_float.patch     | 68 +++++++++++++++++++
 1 file changed, 68 insertions(+)
 create mode 100644 package/devel/valgrind/patches/130-mips_fix_soft_float.patch
diff mbox series

Patch

diff --git a/package/devel/valgrind/patches/130-mips_fix_soft_float.patch b/package/devel/valgrind/patches/130-mips_fix_soft_float.patch
new file mode 100644
index 000000000000..05be099ca5e4
--- /dev/null
+++ b/package/devel/valgrind/patches/130-mips_fix_soft_float.patch
@@ -0,0 +1,68 @@ 
+Disable the valgrind helpers which use MIPS floating point operations 
+when floating point support is deactivated in the toolchain.
+
+The fix from this commit is not sufficient any more:
+https://sourceware.org/git/?p=valgrind.git;a=commitdiff;h=869fcf2f6739f17b4eff36ec68f8dca826c8afeb
+
+This fixes the following error message when compiling with a GCC 10 MIPS BE 32:
+---------------------------------------------------------
+../VEX/priv/guest_mips_helpers.c: In function 'mips_dirtyhelper_calculate_FCSR_fp32':
+../VEX/priv/guest_mips_helpers.c:640:10: error: the register '$f21' cannot be clobbered in 'asm' for the current target
+  640 |          ASM_VOLATILE_UNARY32_DOUBLE(round.w.d)
+      |          ^
+---------------------------------------------------------
+
+--- a/VEX/priv/guest_mips_helpers.c
++++ b/VEX/priv/guest_mips_helpers.c
+@@ -617,6 +617,7 @@ extern UInt mips_dirtyhelper_calculate_F
+                                                    flt_op inst )
+ {
+    UInt ret = 0;
++#ifndef __mips_soft_float
+ #if defined(__mips__)
+    VexGuestMIPS32State* guest_state = (VexGuestMIPS32State*)gs;
+    UInt loFsVal, hiFsVal, loFtVal, hiFtVal;
+@@ -699,6 +700,7 @@ extern UInt mips_dirtyhelper_calculate_F
+          break;
+    }
+ #endif
++#endif
+    return ret;
+ }
+ 
+@@ -708,6 +710,7 @@ extern UInt mips_dirtyhelper_calculate_F
+                                                    flt_op inst )
+ {
+    UInt ret = 0;
++#ifndef __mips_soft_float
+ #if defined(__mips__) && ((__mips == 64) ||                                  \
+                           (defined(__mips_isa_rev) && (__mips_isa_rev >= 2)))
+ #if defined(VGA_mips32)
+@@ -860,6 +863,7 @@ extern UInt mips_dirtyhelper_calculate_F
+          break;
+    }
+ #endif
++#endif
+    return ret;
+ }
+ 
+--- a/coregrind/m_machine.c
++++ b/coregrind/m_machine.c
+@@ -1828,6 +1828,7 @@ Bool VG_(machine_get_hwcaps)( void )
+            we are using alternative way to determine FP mode */
+         ULong result = 0;
+ 
++#ifndef __mips_soft_float
+         if (!VG_MINIMAL_SETJMP(env_unsup_insn)) {
+            __asm__ volatile (
+               ".set push\n\t"
+@@ -1845,6 +1846,9 @@ Bool VG_(machine_get_hwcaps)( void )
+ 
+            fpmode = (result != 0x3FF0000000000000ull);
+         }
++#else
++	fpmode = 0;
++#endif
+      }
+ 
+      if (fpmode != 0)