new file mode 100644
@@ -0,0 +1,599 @@
+CONFIG_ADVISE_SYSCALLS=y
+# CONFIG_AHCI_SUNXI is not set
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_APM_EMULATION is not set
+# CONFIG_ARCH_ALPINE is not set
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+CONFIG_ARCH_HAS_SG_CHAIN=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+# CONFIG_ARCH_MULTI_CPU_AUTO is not set
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NR_GPIO=416
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+CONFIG_ARCH_SUNXI=y
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+CONFIG_ARM=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
+CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_ARM_CCI=y
+CONFIG_ARM_CCI400_COMMON=y
+CONFIG_ARM_CCI400_PMU=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_CRYPTO=y
+CONFIG_ARM_ERRATA_643719=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_HAS_SG_CHAIN=y
+# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+# CONFIG_ARM_LPAE is not set
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_PSCI=y
+CONFIG_ARM_THUMB=y
+# CONFIG_ARM_THUMBEE is not set
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_ATA=y
+CONFIG_ATAGS=y
+# CONFIG_ATA_SFF is not set
+CONFIG_AUDIT=y
+# CONFIG_AUDITSYSCALL is not set
+CONFIG_AUDIT_GENERIC=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_AVERAGE=y
+CONFIG_B53=y
+# CONFIG_B53_MMAP_DRIVER is not set
+CONFIG_B53_PHY_DRIVER=y
+CONFIG_B53_PHY_FIXUP=y
+# CONFIG_B53_SRAB_DRIVER is not set
+# CONFIG_BACKLIGHT_ADP8860 is not set
+# CONFIG_BACKLIGHT_ADP8870 is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_BINFMT_MISC=y
+CONFIG_BLK_CGROUP=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_BOUNCE=y
+# CONFIG_BPF_SYSCALL is not set
+CONFIG_BUILD_BIN2C=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CFQ_GROUP_IOSCHED=y
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_FREEZER=y
+# CONFIG_CGROUP_NET_CLASSID is not set
+# CONFIG_CGROUP_PERF is not set
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLKSRC_OF=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk rootwait root=/dev/mmcblk0p2"
+CONFIG_CMDLINE_FORCE=y
+CONFIG_COMMON_CLK=y
+# CONFIG_COMMON_CLK_PWM is not set
+CONFIG_COMPACTION=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CONNECTOR=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_COREDUMP=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUSETS=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+CONFIG_CPU_HAS_ASID=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRYPTO_ABLK_HELPER=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_AES_ARM=y
+CONFIG_CRYPTO_AES_ARM_CE=y
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_DEV_SUNXI_SS=y
+CONFIG_CRYPTO_GHASH_ARM_CE=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA1_ARM=y
+CONFIG_CRYPTO_SHA1_ARM_CE=y
+CONFIG_CRYPTO_SHA1_ARM_NEON=y
+CONFIG_CRYPTO_SHA256_ARM=y
+CONFIG_CRYPTO_SHA2_ARM_CE=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_SHA512_ARM_NEON=y
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_DCACHE_WORD_ACCESS=y
+# CONFIG_DEBUG_BLK_CGROUP is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_UART_8250 is not set
+# CONFIG_DEBUG_USER is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_DIRECT_IO=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_SUN6I=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DNOTIFY=y
+CONFIG_DTC=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_EEPROM_SUNXI_SID=y
+CONFIG_ELF_CORE=y
+# CONFIG_EMBEDDED is not set
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_EXPERT is not set
+CONFIG_EXT4_FS=y
+CONFIG_FB=y
+# CONFIG_FB_BIG_ENDIAN is not set
+CONFIG_FB_BOTH_ENDIAN=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_FOREIGN_ENDIAN=y
+# CONFIG_FB_LITTLE_ENDIAN is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_SIMPLE=y
+CONFIG_FB_TILEBLITTING=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x16=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_SUPPORT=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FRAME_WARN=2048
+CONFIG_FREEZER=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_DEVRES=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+CONFIG_HAVE_ARCH_BITREVERSE=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_ARM_ARCH_TIMER=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_BPF_JIT=y
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZ4=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_HAVE_KERNEL_XZ=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_OPTPROBES=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_SMP=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_UID16=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HWMON=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_TIMERIOMEM=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_MV64XXX=y
+# CONFIG_I2C_SUN6I_P2WI is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_INPUT_AXP20X_PEK=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_IOMMU_HELPER=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_IPC_NS=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+CONFIG_KALLSYMS=y
+# CONFIG_KEYBOARD_GPIO is not set
+CONFIG_KEYBOARD_SUN4I_LRADC=y
+CONFIG_KSM=y
+# CONFIG_LCD_AMS369FG06 is not set
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_L4F00242T03 is not set
+# CONFIG_LCD_LD9040 is not set
+# CONFIG_LCD_LMS283GF05 is not set
+# CONFIG_LCD_LTV350QV is not set
+CONFIG_LCD_PLATFORM=y
+# CONFIG_LCD_S6E63M0 is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_REGULATOR is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_LIBFDT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOG_BUF_SHIFT=19
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MACH_SUN4I=y
+CONFIG_MACH_SUN5I=y
+CONFIG_MACH_SUN6I=y
+CONFIG_MACH_SUN7I=y
+# CONFIG_MACH_SUN8I is not set
+# CONFIG_MACH_SUN9I is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MDIO_BOARDINFO=y
+CONFIG_MDIO_SUN4I=y
+# CONFIG_MEMCG is not set
+CONFIG_MFD_AXP20X=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_SUN6I_PRCM=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGHT_HAVE_PCI=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+CONFIG_MMC_SUNXI=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MULTI_IRQ_HANDLER=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NAMESPACES=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEON=y
+# CONFIG_NET_CLS_CGROUP is not set
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_NS=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_VENDOR_ALLWINNER=y
+CONFIG_NLS=y
+CONFIG_NO_BOOTMEM=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=4
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_MTD=y
+CONFIG_OF_NET=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_OF_TOUCHSCREEN=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PARTITION_ADVANCED is not set
+# CONFIG_PCI is not set
+# CONFIG_PCI_DOMAINS_GENERIC is not set
+# CONFIG_PCI_SYSCALL is not set
+CONFIG_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHY_SUN4I_USB=y
+# CONFIG_PHY_SUN9I_USB is not set
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PINCTRL_SUN4I_A10=y
+CONFIG_PINCTRL_SUN5I_A10S=y
+CONFIG_PINCTRL_SUN5I_A13=y
+CONFIG_PINCTRL_SUN6I_A31=y
+CONFIG_PINCTRL_SUN6I_A31S=y
+CONFIG_PINCTRL_SUN6I_A31_R=y
+CONFIG_PINCTRL_SUN7I_A20=y
+# CONFIG_PINCTRL_SUN8I_A23 is not set
+# CONFIG_PINCTRL_SUN8I_A23_R is not set
+# CONFIG_PINCTRL_SUN9I_A80 is not set
+CONFIG_PINCTRL_SUNXI_COMMON=y
+# CONFIG_PL310_ERRATA_588369 is not set
+# CONFIG_PL310_ERRATA_727915 is not set
+# CONFIG_PL310_ERRATA_753970 is not set
+# CONFIG_PL310_ERRATA_769419 is not set
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_OPP=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_POWER_RESET=y
+# CONFIG_POWER_RESET_GPIO is not set
+# CONFIG_POWER_RESET_GPIO_RESTART is not set
+# CONFIG_POWER_RESET_LTC2952 is not set
+# CONFIG_POWER_RESET_SYSCON is not set
+# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PREEMPT=y
+CONFIG_PREEMPT_COUNT=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_RCU=y
+CONFIG_PRINTK_TIME=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+CONFIG_PROC_EVENTS=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PWM=y
+# CONFIG_PWM_FSL_FTM is not set
+CONFIG_PWM_SUN4I=y
+CONFIG_PWM_SYSFS=y
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+# CONFIG_QORIQ_CPUFREQ is not set
+CONFIG_QUOTA=y
+CONFIG_QUOTACTL=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_RCU_BOOST is not set
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_IRQ=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_AXP20X=y
+# CONFIG_REGULATOR_DEBUG is not set
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+# CONFIG_REGULATOR_PWM is not set
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+CONFIG_RELAY=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_SATA_PMP=y
+CONFIG_SCHED_HRTICK=y
+CONFIG_SCSI=y
+CONFIG_SDIO_UART=y
+CONFIG_SECURITYFS=y
+# CONFIG_SENSORS_PWM_FAN is not set
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_NR_UARTS=8
+CONFIG_SERIAL_8250_RUNTIME_UARTS=8
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIO=y
+# CONFIG_SERIO_APBPS2 is not set
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_SUN4I_PS2 is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+CONFIG_SLUB_CPU_PARTIAL=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLUB_DEBUG_ON is not set
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_SUN4I=y
+CONFIG_SPI_SUN6I=y
+CONFIG_SRCU=y
+# CONFIG_STAGING is not set
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_PLATFORM=y
+CONFIG_STOP_MACHINE=y
+CONFIG_STRICT_DEVMEM=y
+# CONFIG_SUN4I_EMAC is not set
+CONFIG_SUN4I_TIMER=y
+CONFIG_SUN5I_HSTIMER=y
+CONFIG_SUNXI_WATCHDOG=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SWCONFIG=y
+CONFIG_SWIOTLB=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_TASK_XACCT=y
+CONFIG_THERMAL=y
+# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
+# CONFIG_THERMAL_EMULATION is not set
+# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
+CONFIG_THERMAL_GOV_STEP_WISE=y
+# CONFIG_THERMAL_GOV_USER_SPACE is not set
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set
+# CONFIG_TOUCHSCREEN_ELAN is not set
+# CONFIG_TOUCHSCREEN_GOODIX is not set
+CONFIG_TOUCHSCREEN_SUN4I=y
+# CONFIG_TOUCHSCREEN_SX8654 is not set
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_UID16=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_DWC2=y
+# CONFIG_USB_DWC2_DEBUG is not set
+CONFIG_USB_DWC2_HOST=y
+CONFIG_USB_DWC2_PLATFORM=y
+# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_NET_DRIVERS=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USELIB=y
+# CONFIG_USER_NS is not set
+CONFIG_USE_OF=y
+CONFIG_UTS_NS=y
+CONFIG_VDSO=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_XFRM_ALGO=y
+CONFIG_XFRM_USER=y
+CONFIG_XPS=y
+CONFIG_XZ_DEC_ARM=y
+# CONFIG_XZ_DEC_ARMTHUMB is not set
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZONE_DMA_FLAG=0
new file mode 100644
@@ -0,0 +1,68 @@
+From e4127db9b980a5684c537d9010ed2aaa05a1e79a Mon Sep 17 00:00:00 2001
+From: Hans de Goede <hdegoede@redhat.com>
+Date: Sat, 24 May 2014 20:53:49 +0200
+Subject: [PATCH] ARM: dts: sun7i: Add OOB irq support to boards with broadcom
+ sdio wifi
+
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+---
+ arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 11 +++++++++++
+ arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts | 11 +++++++++++
+ 2 files changed, 22 insertions(+)
+
+Index: linux-4.1.3/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+===================================================================
+--- linux-4.1.3.orig/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
++++ linux-4.1.3/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+@@ -71,12 +71,23 @@
+ };
+
+ mmc3: mmc@01c12000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc3_pins_a>;
+ vmmc-supply = <®_vmmc3>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
++
++ brcmf: bcrmf@1 {
++ reg = <1>;
++ compatible = "brcm,bcm4329-fmac";
++ interrupt-parent = <&pio>;
++ interrupts = <10 8>; /* PH10 / EINT10 */
++ interrupt-names = "host-wake";
++ };
+ };
+
+ usbphy: phy@01c13400 {
+Index: linux-4.1.3/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
+===================================================================
+--- linux-4.1.3.orig/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
++++ linux-4.1.3/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
+@@ -69,12 +69,23 @@
+ };
+
+ mmc3: mmc@01c12000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc3_pins_a>;
+ vmmc-supply = <®_vmmc3>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
++
++ brcmf: bcrmf@1 {
++ reg = <1>;
++ compatible = "brcm,bcm4329-fmac";
++ interrupt-parent = <&pio>;
++ interrupts = <10 8>; /* PH10 / EINT10 */
++ interrupt-names = "host-wake";
++ };
+ };
+
+ usbphy: phy@01c13400 {
new file mode 100644
@@ -0,0 +1,77 @@
+From c6e2b7dad39a7887f935458d1c8de84db06243e1 Mon Sep 17 00:00:00 2001
+From: Chen-Yu Tsai <wens@csie.org>
+Date: Thu, 26 Dec 2013 17:15:47 +0800
+Subject: [PATCH] ARM: dts: sun7i: add bluetooth module to CubieTruck DTS
+
+The CubieTruck has an AMPAK AP6210 WiFi+Bluetooth module. The
+Bluetooth part is a BCM20710 IC connected to UART2 in the A20
+SoC. The IC also takes a 32.768 KHz low power clock input, a power
+enable signal and a wake signal via GPIO.
+
+The Bluetooth module supports out-of-band interrupt signaling via
+GPIO, but this is not supported in this patch.
+---
+ arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 36 ++++++++++++++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+
+Index: linux-4.1.3/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+===================================================================
+--- linux-4.1.3.orig/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
++++ linux-4.1.3/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+@@ -88,6 +88,20 @@
+ interrupts = <10 8>; /* PH10 / EINT10 */
+ interrupt-names = "host-wake";
+ };
++
++ bt_pwr_pin: bt_pwr_pin@0 {
++ allwinner,pins = "PH18";
++ allwinner,function = "gpio_out";
++ allwinner,drive = <0>;
++ allwinner,pull = <0>;
++ };
++
++ bt_wake_pin: bt_wake_pin@0 {
++ allwinner,pins = "PH24";
++ allwinner,function = "gpio_out";
++ allwinner,drive = <0>;
++ allwinner,pull = <0>;
++ };
+ };
+
+ usbphy: phy@01c13400 {
+@@ -171,6 +185,12 @@
+ status = "okay";
+ };
+
++ uart2: serial@01c28800 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart2_pins_a>;
++ status = "okay";
++ };
++
+ i2c0: i2c@01c2ac00 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+@@ -264,6 +284,22 @@
+ enable-active-high;
+ gpio = <&pio 7 9 GPIO_ACTIVE_HIGH>;
+ };
++
++ rfkill-switches {
++ compatible = "simple-bus";
++ pinctrl-names = "default";
++
++ rfkill_bt {
++ compatible = "rfkill-gpio";
++ pinctrl-0 = <&bt_pwr_pin>, <&clk_out_a_pins_a>;
++ rfkill-name = "bt";
++ rfkill-type = <2>;
++ bt_shutdown-gpios = <0>, <&pio 7 18 0>; /* PH18 */
++ bt_reset-gpios = <&pio 7 24 0>; /* PH24 */
++ clocks = <&clk_out_a>;
++ clock-frequency = <32768>;
++ };
++ };
+ };
+
+ #include "axp209.dtsi"
new file mode 100644
@@ -0,0 +1,19 @@
+Index: linux-4.1.3/arch/arm/boot/dts/sun7i-a20.dtsi
+===================================================================
+--- linux-4.1.3.orig/arch/arm/boot/dts/sun7i-a20.dtsi
++++ linux-4.1.3/arch/arm/boot/dts/sun7i-a20.dtsi
+@@ -679,6 +679,14 @@
+ status = "disabled";
+ };
+
++ crypto: crypto-engine@01c15000 {
++ compatible = "allwinner,sun7i-a20-crypto";
++ reg = <0x01c15000 0x1000>;
++ interrupts = <0 86 4>;
++ clocks = <&ahb_gates 5>, <&ss_clk>;
++ clock-names = "ahb", "mod";
++ };
++
+ spi2: spi@01c17000 {
+ compatible = "allwinner,sun4i-a10-spi";
+ reg = <0x01c17000 0x1000>;
new file mode 100644
@@ -0,0 +1,1508 @@
+Index: linux-4.1.3/drivers/crypto/Kconfig
+===================================================================
+--- linux-4.1.3.orig/drivers/crypto/Kconfig
++++ linux-4.1.3/drivers/crypto/Kconfig
+@@ -460,4 +460,21 @@ config CRYPTO_DEV_IMGTEC_HASH
+ hardware hash accelerator. Supporting MD5/SHA1/SHA224/SHA256
+ hashing algorithms.
+
++config CRYPTO_DEV_SUNXI_SS
++ tristate "Support for Allwinner Security System cryptographic accelerator"
++ depends on ARCH_SUNXI
++ select CRYPTO_MD5
++ select CRYPTO_SHA1
++ select CRYPTO_AES
++ select CRYPTO_DES
++ select CRYPTO_BLKCIPHER
++ help
++ Some Allwinner SoC have a crypto accelerator named
++ Security System. Select this if you want to use it.
++ The Security System handle AES/DES/3DES ciphers in CBC mode
++ and SHA1 and MD5 hash algorithms.
++
++ To compile this driver as a module, choose M here: the module
++ will be called sunxi-ss.
++
+ endif # CRYPTO_HW
+Index: linux-4.1.3/drivers/crypto/Makefile
+===================================================================
+--- linux-4.1.3.orig/drivers/crypto/Makefile
++++ linux-4.1.3/drivers/crypto/Makefile
+@@ -26,4 +26,5 @@ obj-$(CONFIG_CRYPTO_DEV_TALITOS) += tali
+ obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/
+ obj-$(CONFIG_CRYPTO_DEV_QAT) += qat/
+ obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/
++obj-$(CONFIG_CRYPTO_DEV_SUNXI_SS) += sunxi-ss/
+ obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
+Index: linux-4.1.3/drivers/crypto/sunxi-ss/Makefile
+===================================================================
+--- /dev/null
++++ linux-4.1.3/drivers/crypto/sunxi-ss/Makefile
+@@ -0,0 +1,2 @@
++obj-$(CONFIG_CRYPTO_DEV_SUNXI_SS) += sunxi-ss.o
++sunxi-ss-y += sunxi-ss-core.o sunxi-ss-hash.o sunxi-ss-cipher.o
+Index: linux-4.1.3/drivers/crypto/sunxi-ss/sunxi-ss-cipher.c
+===================================================================
+--- /dev/null
++++ linux-4.1.3/drivers/crypto/sunxi-ss/sunxi-ss-cipher.c
+@@ -0,0 +1,489 @@
++/*
++ * sunxi-ss-cipher.c - hardware cryptographic accelerator for Allwinner A20 SoC
++ *
++ * Copyright (C) 2013-2014 Corentin LABBE <clabbe.montjoie@gmail.com>
++ *
++ * This file add support for AES cipher with 128,192,256 bits
++ * keysize in CBC mode.
++ * Add support also for DES and 3DES in CBC mode.
++ *
++ * You could find the datasheet in Documentation/arm/sunxi/README
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++#include "sunxi-ss.h"
++
++extern struct sunxi_ss_ctx *ss;
++
++static int sunxi_ss_cipher(struct ablkcipher_request *areq, u32 mode)
++{
++ struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
++ struct sunxi_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
++ const char *cipher_type;
++
++ if (areq->nbytes == 0)
++ return 0;
++
++ if (areq->info == NULL) {
++ dev_err(ss->dev, "ERROR: Empty IV\n");
++ return -EINVAL;
++ }
++
++ if (areq->src == NULL || areq->dst == NULL) {
++ dev_err(ss->dev, "ERROR: Some SGs are NULL\n");
++ return -EINVAL;
++ }
++
++ cipher_type = crypto_tfm_alg_name(crypto_ablkcipher_tfm(tfm));
++
++ if (strcmp("cbc(aes)", cipher_type) == 0) {
++ mode |= SS_OP_AES | SS_CBC | SS_ENABLED | op->keymode;
++ return sunxi_ss_aes_poll(areq, mode);
++ }
++
++ if (strcmp("cbc(des)", cipher_type) == 0) {
++ mode |= SS_OP_DES | SS_CBC | SS_ENABLED | op->keymode;
++ return sunxi_ss_des_poll(areq, mode);
++ }
++
++ if (strcmp("cbc(des3_ede)", cipher_type) == 0) {
++ mode |= SS_OP_3DES | SS_CBC | SS_ENABLED | op->keymode;
++ return sunxi_ss_des_poll(areq, mode);
++ }
++
++ dev_err(ss->dev, "ERROR: Cipher %s not handled\n", cipher_type);
++ return -EINVAL;
++}
++
++int sunxi_ss_cipher_encrypt(struct ablkcipher_request *areq)
++{
++ return sunxi_ss_cipher(areq, SS_ENCRYPTION);
++}
++
++int sunxi_ss_cipher_decrypt(struct ablkcipher_request *areq)
++{
++ return sunxi_ss_cipher(areq, SS_DECRYPTION);
++}
++
++int sunxi_ss_cipher_init(struct crypto_tfm *tfm)
++{
++ struct sunxi_tfm_ctx *op = crypto_tfm_ctx(tfm);
++
++ memset(op, 0, sizeof(struct sunxi_tfm_ctx));
++ return 0;
++}
++
++/*
++ * Optimized function for the case where we have only one SG,
++ * so we can use kmap_atomic
++ */
++static int sunxi_ss_aes_poll_atomic(struct ablkcipher_request *areq)
++{
++ u32 spaces;
++ struct scatterlist *in_sg = areq->src;
++ struct scatterlist *out_sg = areq->dst;
++ void *src_addr;
++ void *dst_addr;
++ unsigned int ileft = areq->nbytes;
++ unsigned int oleft = areq->nbytes;
++ unsigned int todo;
++ u32 *src32;
++ u32 *dst32;
++ u32 rx_cnt = 32;
++ u32 tx_cnt = 0;
++ int i;
++
++ src_addr = kmap_atomic(sg_page(in_sg)) + in_sg->offset;
++ if (src_addr == NULL) {
++ dev_err(ss->dev, "kmap_atomic error for src SG\n");
++ writel(0, ss->base + SS_CTL);
++ mutex_unlock(&ss->lock);
++ return -EINVAL;
++ }
++
++ dst_addr = kmap_atomic(sg_page(out_sg)) + out_sg->offset;
++ if (dst_addr == NULL) {
++ dev_err(ss->dev, "kmap_atomic error for dst SG\n");
++ writel(0, ss->base + SS_CTL);
++ kunmap_atomic(src_addr);
++ mutex_unlock(&ss->lock);
++ return -EINVAL;
++ }
++
++ src32 = (u32 *)src_addr;
++ dst32 = (u32 *)dst_addr;
++ ileft = areq->nbytes / 4;
++ oleft = areq->nbytes / 4;
++ i = 0;
++ do {
++ if (ileft > 0 && rx_cnt > 0) {
++ todo = min(rx_cnt, ileft);
++ ileft -= todo;
++ do {
++ writel_relaxed(*src32++,
++ ss->base +
++ SS_RXFIFO);
++ todo--;
++ } while (todo > 0);
++ }
++ if (tx_cnt > 0) {
++ todo = min(tx_cnt, oleft);
++ oleft -= todo;
++ do {
++ *dst32++ = readl_relaxed(ss->base +
++ SS_TXFIFO);
++ todo--;
++ } while (todo > 0);
++ }
++ spaces = readl_relaxed(ss->base + SS_FCSR);
++ rx_cnt = SS_RXFIFO_SPACES(spaces);
++ tx_cnt = SS_TXFIFO_SPACES(spaces);
++ } while (oleft > 0);
++ writel(0, ss->base + SS_CTL);
++ kunmap_atomic(src_addr);
++ kunmap_atomic(dst_addr);
++ mutex_unlock(&ss->lock);
++ return 0;
++}
++
++int sunxi_ss_aes_poll(struct ablkcipher_request *areq, u32 mode)
++{
++ u32 spaces;
++ struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
++ struct sunxi_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
++ unsigned int ivsize = crypto_ablkcipher_ivsize(tfm);
++ /* when activating SS, the default FIFO space is 32 */
++ u32 rx_cnt = 32;
++ u32 tx_cnt = 0;
++ u32 v;
++ int i;
++ struct scatterlist *in_sg = areq->src;
++ struct scatterlist *out_sg = areq->dst;
++ void *src_addr;
++ void *dst_addr;
++ unsigned int ileft = areq->nbytes;
++ unsigned int oleft = areq->nbytes;
++ unsigned int sgileft = areq->src->length;
++ unsigned int sgoleft = areq->dst->length;
++ unsigned int todo;
++ u32 *src32;
++ u32 *dst32;
++
++ mutex_lock(&ss->lock);
++
++ for (i = 0; i < op->keylen; i += 4)
++ writel(*(op->key + i/4), ss->base + SS_KEY0 + i);
++
++ if (areq->info != NULL) {
++ for (i = 0; i < 4 && i < ivsize / 4; i++) {
++ v = *(u32 *)(areq->info + i * 4);
++ writel(v, ss->base + SS_IV0 + i * 4);
++ }
++ }
++ writel(mode, ss->base + SS_CTL);
++
++ /* If we have only one SG, we can use kmap_atomic */
++ if (sg_next(in_sg) == NULL && sg_next(out_sg) == NULL)
++ return sunxi_ss_aes_poll_atomic(areq);
++
++ /*
++ * If we have more than one SG, we cannot use kmap_atomic since
++ * we hold the mapping too long
++ */
++ src_addr = kmap(sg_page(in_sg)) + in_sg->offset;
++ if (src_addr == NULL) {
++ dev_err(ss->dev, "KMAP error for src SG\n");
++ mutex_unlock(&ss->lock);
++ return -EINVAL;
++ }
++ dst_addr = kmap(sg_page(out_sg)) + out_sg->offset;
++ if (dst_addr == NULL) {
++ kunmap(sg_page(in_sg));
++ dev_err(ss->dev, "KMAP error for dst SG\n");
++ mutex_unlock(&ss->lock);
++ return -EINVAL;
++ }
++ src32 = (u32 *)src_addr;
++ dst32 = (u32 *)dst_addr;
++ ileft = areq->nbytes / 4;
++ oleft = areq->nbytes / 4;
++ sgileft = in_sg->length / 4;
++ sgoleft = out_sg->length / 4;
++ do {
++ spaces = readl_relaxed(ss->base + SS_FCSR);
++ rx_cnt = SS_RXFIFO_SPACES(spaces);
++ tx_cnt = SS_TXFIFO_SPACES(spaces);
++ todo = min3(rx_cnt, ileft, sgileft);
++ if (todo > 0) {
++ ileft -= todo;
++ sgileft -= todo;
++ }
++ while (todo > 0) {
++ writel_relaxed(*src32++, ss->base + SS_RXFIFO);
++ todo--;
++ }
++ if (in_sg != NULL && sgileft == 0 && ileft > 0) {
++ kunmap(sg_page(in_sg));
++ in_sg = sg_next(in_sg);
++ while (in_sg != NULL && in_sg->length == 0)
++ in_sg = sg_next(in_sg);
++ if (in_sg != NULL && ileft > 0) {
++ src_addr = kmap(sg_page(in_sg)) + in_sg->offset;
++ if (src_addr == NULL) {
++ dev_err(ss->dev, "ERROR: KMAP for src SG\n");
++ mutex_unlock(&ss->lock);
++ return -EINVAL;
++ }
++ src32 = src_addr;
++ sgileft = in_sg->length / 4;
++ }
++ }
++ /* do not test oleft since when oleft == 0 we have finished */
++ todo = min3(tx_cnt, oleft, sgoleft);
++ if (todo > 0) {
++ oleft -= todo;
++ sgoleft -= todo;
++ }
++ while (todo > 0) {
++ *dst32++ = readl_relaxed(ss->base + SS_TXFIFO);
++ todo--;
++ }
++ if (out_sg != NULL && sgoleft == 0 && oleft >= 0) {
++ kunmap(sg_page(out_sg));
++ out_sg = sg_next(out_sg);
++ while (out_sg != NULL && out_sg->length == 0)
++ out_sg = sg_next(out_sg);
++ if (out_sg != NULL && oleft > 0) {
++ dst_addr = kmap(sg_page(out_sg)) +
++ out_sg->offset;
++ if (dst_addr == NULL) {
++ dev_err(ss->dev, "KMAP error\n");
++ mutex_unlock(&ss->lock);
++ return -EINVAL;
++ }
++ dst32 = dst_addr;
++ sgoleft = out_sg->length / 4;
++ }
++ }
++ } while (oleft > 0);
++
++ writel_relaxed(0, ss->base + SS_CTL);
++ mutex_unlock(&ss->lock);
++ return 0;
++}
++
++/*
++ * Pure CPU way of doing DES/3DES with SS
++ * Since DES and 3DES SGs could be smaller than 4 bytes, I use sg_copy_to_buffer
++ * for "linearize" them.
++ * The problem with that is that I alloc (2 x areq->nbytes) for buf_in/buf_out
++ * TODO: change this system, I need to support other mode than CBC where len
++ * is not a multiple of 4 and the hack of linearize use too much memory
++ * SGsrc -> buf_in -> SS -> buf_out -> SGdst
++ */
++int sunxi_ss_des_poll(struct ablkcipher_request *areq, u32 mode)
++{
++ u32 value, spaces;
++ size_t nb_in_sg_tx, nb_in_sg_rx;
++ size_t ir, it;
++ struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
++ struct sunxi_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
++ unsigned int ivsize = crypto_ablkcipher_ivsize(tfm);
++ u32 tx_cnt = 0;
++ u32 rx_cnt = 0;
++ u32 v;
++ int i;
++ int no_chunk = 1;
++ struct scatterlist *in_sg = areq->src;
++ struct scatterlist *out_sg = areq->dst;
++
++ /*
++ * if we have only SGs with size multiple of 4,
++ * we can use the SS AES function
++ */
++ while (in_sg != NULL && no_chunk == 1) {
++ if ((in_sg->length % 4) != 0)
++ no_chunk = 0;
++ in_sg = sg_next(in_sg);
++ }
++ while (out_sg != NULL && no_chunk == 1) {
++ if ((out_sg->length % 4) != 0)
++ no_chunk = 0;
++ out_sg = sg_next(out_sg);
++ }
++
++ if (no_chunk == 1)
++ return sunxi_ss_aes_poll(areq, mode);
++
++ in_sg = areq->src;
++ out_sg = areq->dst;
++
++ nb_in_sg_rx = sg_nents(in_sg);
++ nb_in_sg_tx = sg_nents(out_sg);
++
++ /*
++ * buf_in and buf_out are allocated only one time
++ * then we keep the buffer until driver end
++ * the allocation can only grow more
++ * we do not reduce it for simplification
++ */
++ mutex_lock(&ss->bufin_lock);
++ if (ss->buf_in == NULL) {
++ ss->buf_in = kmalloc(areq->nbytes, GFP_KERNEL);
++ ss->buf_in_size = areq->nbytes;
++ } else {
++ if (areq->nbytes > ss->buf_in_size) {
++ kfree(ss->buf_in);
++ ss->buf_in = kmalloc(areq->nbytes, GFP_KERNEL);
++ ss->buf_in_size = areq->nbytes;
++ }
++ }
++ if (ss->buf_in == NULL) {
++ ss->buf_in_size = 0;
++ mutex_unlock(&ss->bufin_lock);
++ dev_err(ss->dev, "Unable to allocate pages.\n");
++ return -ENOMEM;
++ }
++ mutex_lock(&ss->bufout_lock);
++ if (ss->buf_out == NULL) {
++ ss->buf_out = kmalloc(areq->nbytes, GFP_KERNEL);
++ if (ss->buf_out == NULL) {
++ ss->buf_out_size = 0;
++ mutex_unlock(&ss->bufin_lock);
++ mutex_unlock(&ss->bufout_lock);
++ dev_err(ss->dev, "Unable to allocate pages.\n");
++ return -ENOMEM;
++ }
++ ss->buf_out_size = areq->nbytes;
++ } else {
++ if (areq->nbytes > ss->buf_out_size) {
++ kfree(ss->buf_out);
++ ss->buf_out = kmalloc(areq->nbytes, GFP_KERNEL);
++ if (ss->buf_out == NULL) {
++ ss->buf_out_size = 0;
++ mutex_unlock(&ss->bufin_lock);
++ mutex_unlock(&ss->bufout_lock);
++ dev_err(ss->dev, "Unable to allocate pages.\n");
++ return -ENOMEM;
++ }
++ ss->buf_out_size = areq->nbytes;
++ }
++ }
++
++ sg_copy_to_buffer(areq->src, nb_in_sg_rx, ss->buf_in, areq->nbytes);
++
++ ir = 0;
++ it = 0;
++ mutex_lock(&ss->lock);
++
++ for (i = 0; i < op->keylen; i += 4)
++ writel(*(op->key + i/4), ss->base + SS_KEY0 + i);
++ if (areq->info != NULL) {
++ for (i = 0; i < 4 && i < ivsize / 4; i++) {
++ v = *(u32 *)(areq->info + i * 4);
++ writel(v, ss->base + SS_IV0 + i * 4);
++ }
++ }
++ writel(mode, ss->base + SS_CTL);
++
++ do {
++ if (rx_cnt == 0 || tx_cnt == 0) {
++ spaces = readl(ss->base + SS_FCSR);
++ rx_cnt = SS_RXFIFO_SPACES(spaces);
++ tx_cnt = SS_TXFIFO_SPACES(spaces);
++ }
++ if (rx_cnt > 0 && ir < areq->nbytes) {
++ do {
++ value = *(u32 *)(ss->buf_in + ir);
++ writel(value, ss->base + SS_RXFIFO);
++ ir += 4;
++ rx_cnt--;
++ } while (rx_cnt > 0 && ir < areq->nbytes);
++ }
++ if (tx_cnt > 0 && it < areq->nbytes) {
++ do {
++ value = readl(ss->base + SS_TXFIFO);
++ *(u32 *)(ss->buf_out + it) = value;
++ it += 4;
++ tx_cnt--;
++ } while (tx_cnt > 0 && it < areq->nbytes);
++ }
++ if (ir == areq->nbytes) {
++ mutex_unlock(&ss->bufin_lock);
++ ir++;
++ }
++ } while (it < areq->nbytes);
++
++ writel(0, ss->base + SS_CTL);
++ mutex_unlock(&ss->lock);
++
++ /*
++ * a simple optimization, since we dont need the hardware for this copy
++ * we release the lock and do the copy. With that we gain 5/10% perf
++ */
++ sg_copy_from_buffer(areq->dst, nb_in_sg_tx, ss->buf_out, areq->nbytes);
++
++ mutex_unlock(&ss->bufout_lock);
++ return 0;
++}
++
++/* check and set the AES key, prepare the mode to be used */
++int sunxi_ss_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
++ unsigned int keylen)
++{
++ struct sunxi_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
++
++ switch (keylen) {
++ case 128 / 8:
++ op->keymode = SS_AES_128BITS;
++ break;
++ case 192 / 8:
++ op->keymode = SS_AES_192BITS;
++ break;
++ case 256 / 8:
++ op->keymode = SS_AES_256BITS;
++ break;
++ default:
++ dev_err(ss->dev, "ERROR: Invalid keylen %u\n", keylen);
++ crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
++ return -EINVAL;
++ }
++ op->keylen = keylen;
++ memcpy(op->key, key, keylen);
++ return 0;
++}
++
++/* check and set the DES key, prepare the mode to be used */
++int sunxi_ss_des_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
++ unsigned int keylen)
++{
++ struct sunxi_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
++
++ if (keylen != DES_KEY_SIZE) {
++ dev_err(ss->dev, "Invalid keylen %u\n", keylen);
++ crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
++ return -EINVAL;
++ }
++ op->keylen = keylen;
++ memcpy(op->key, key, keylen);
++ return 0;
++}
++
++/* check and set the 3DES key, prepare the mode to be used */
++int sunxi_ss_des3_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
++ unsigned int keylen)
++{
++ struct sunxi_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
++
++ if (keylen != 3 * DES_KEY_SIZE) {
++ dev_err(ss->dev, "Invalid keylen %u\n", keylen);
++ crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
++ return -EINVAL;
++ }
++ op->keylen = keylen;
++ memcpy(op->key, key, keylen);
++ return 0;
++}
+Index: linux-4.1.3/drivers/crypto/sunxi-ss/sunxi-ss-core.c
+===================================================================
+--- /dev/null
++++ linux-4.1.3/drivers/crypto/sunxi-ss/sunxi-ss-core.c
+@@ -0,0 +1,318 @@
++/*
++ * sunxi-ss-core.c - hardware cryptographic accelerator for Allwinner A20 SoC
++ *
++ * Copyright (C) 2013-2014 Corentin LABBE <clabbe.montjoie@gmail.com>
++ *
++ * Core file which registers crypto algorithms supported by the SS.
++ *
++ * You could find a link for the datasheet in Documentation/arm/sunxi/README
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++#include <linux/clk.h>
++#include <linux/crypto.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <crypto/scatterwalk.h>
++#include <linux/scatterlist.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++
++#include "sunxi-ss.h"
++
++struct sunxi_ss_ctx *ss;
++
++/*
++ * General notes for whole driver:
++ *
++ * After each request the device must be disabled with a write of 0 in SS_CTL
++ *
++ * For performance reason, we use writel_relaxed/read_relaxed for all
++ * operations on RX and TX FIFO and also SS_FCSR.
++ * Excepts for the last write on TX FIFO.
++ * For all other registers, we use writel/readl.
++ * See http://permalink.gmane.org/gmane.linux.ports.arm.kernel/117644
++ * and http://permalink.gmane.org/gmane.linux.ports.arm.kernel/117640
++ */
++
++static struct ahash_alg sunxi_md5_alg = {
++ .init = sunxi_hash_init,
++ .update = sunxi_hash_update,
++ .final = sunxi_hash_final,
++ .finup = sunxi_hash_finup,
++ .digest = sunxi_hash_digest,
++ .halg = {
++ .digestsize = MD5_DIGEST_SIZE,
++ .base = {
++ .cra_name = "md5",
++ .cra_driver_name = "md5-sunxi-ss",
++ .cra_priority = 300,
++ .cra_alignmask = 3,
++ .cra_flags = CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
++ .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
++ .cra_ctxsize = sizeof(struct sunxi_req_ctx),
++ .cra_module = THIS_MODULE,
++ .cra_type = &crypto_ahash_type,
++ .cra_init = sunxi_hash_crainit
++ }
++ }
++};
++
++static struct ahash_alg sunxi_sha1_alg = {
++ .init = sunxi_hash_init,
++ .update = sunxi_hash_update,
++ .final = sunxi_hash_final,
++ .finup = sunxi_hash_finup,
++ .digest = sunxi_hash_digest,
++ .halg = {
++ .digestsize = SHA1_DIGEST_SIZE,
++ .base = {
++ .cra_name = "sha1",
++ .cra_driver_name = "sha1-sunxi-ss",
++ .cra_priority = 300,
++ .cra_alignmask = 3,
++ .cra_flags = CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
++ .cra_blocksize = SHA1_BLOCK_SIZE,
++ .cra_ctxsize = sizeof(struct sunxi_req_ctx),
++ .cra_module = THIS_MODULE,
++ .cra_type = &crypto_ahash_type,
++ .cra_init = sunxi_hash_crainit
++ }
++ }
++};
++
++static struct crypto_alg sunxi_cipher_algs[] = {
++{
++ .cra_name = "cbc(aes)",
++ .cra_driver_name = "cbc-aes-sunxi-ss",
++ .cra_priority = 300,
++ .cra_blocksize = AES_BLOCK_SIZE,
++ .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
++ .cra_ctxsize = sizeof(struct sunxi_tfm_ctx),
++ .cra_module = THIS_MODULE,
++ .cra_alignmask = 3,
++ .cra_type = &crypto_ablkcipher_type,
++ .cra_init = sunxi_ss_cipher_init,
++ .cra_u = {
++ .ablkcipher = {
++ .min_keysize = AES_MIN_KEY_SIZE,
++ .max_keysize = AES_MAX_KEY_SIZE,
++ .ivsize = AES_BLOCK_SIZE,
++ .setkey = sunxi_ss_aes_setkey,
++ .encrypt = sunxi_ss_cipher_encrypt,
++ .decrypt = sunxi_ss_cipher_decrypt,
++ }
++ }
++}, {
++ .cra_name = "cbc(des)",
++ .cra_driver_name = "cbc-des-sunxi-ss",
++ .cra_priority = 300,
++ .cra_blocksize = DES_BLOCK_SIZE,
++ .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
++ .cra_ctxsize = sizeof(struct sunxi_req_ctx),
++ .cra_module = THIS_MODULE,
++ .cra_alignmask = 3,
++ .cra_type = &crypto_ablkcipher_type,
++ .cra_init = sunxi_ss_cipher_init,
++ .cra_u.ablkcipher = {
++ .min_keysize = DES_KEY_SIZE,
++ .max_keysize = DES_KEY_SIZE,
++ .ivsize = DES_BLOCK_SIZE,
++ .setkey = sunxi_ss_des_setkey,
++ .encrypt = sunxi_ss_cipher_encrypt,
++ .decrypt = sunxi_ss_cipher_decrypt,
++ }
++}, {
++ .cra_name = "cbc(des3_ede)",
++ .cra_driver_name = "cbc-des3-sunxi-ss",
++ .cra_priority = 300,
++ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
++ .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
++ .cra_ctxsize = sizeof(struct sunxi_req_ctx),
++ .cra_module = THIS_MODULE,
++ .cra_alignmask = 3,
++ .cra_type = &crypto_ablkcipher_type,
++ .cra_init = sunxi_ss_cipher_init,
++ .cra_u.ablkcipher = {
++ .min_keysize = DES3_EDE_KEY_SIZE,
++ .max_keysize = DES3_EDE_KEY_SIZE,
++ .ivsize = DES3_EDE_BLOCK_SIZE,
++ .setkey = sunxi_ss_des3_setkey,
++ .encrypt = sunxi_ss_cipher_encrypt,
++ .decrypt = sunxi_ss_cipher_decrypt,
++ }
++}
++};
++
++static int sunxi_ss_probe(struct platform_device *pdev)
++{
++ struct resource *res;
++ u32 v;
++ int err;
++ unsigned long cr;
++ const unsigned long cr_ahb = 24 * 1000 * 1000;
++ const unsigned long cr_mod = 150 * 1000 * 1000;
++
++ if (!pdev->dev.of_node)
++ return -ENODEV;
++
++ ss = devm_kzalloc(&pdev->dev, sizeof(*ss), GFP_KERNEL);
++ if (ss == NULL)
++ return -ENOMEM;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ ss->base = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(ss->base)) {
++ dev_err(&pdev->dev, "Cannot request MMIO\n");
++ return PTR_ERR(ss->base);
++ }
++
++ ss->ssclk = devm_clk_get(&pdev->dev, "mod");
++ if (IS_ERR(ss->ssclk)) {
++ err = PTR_ERR(ss->ssclk);
++ dev_err(&pdev->dev, "Cannot get SS clock err=%d\n", err);
++ return err;
++ }
++ dev_dbg(&pdev->dev, "clock ss acquired\n");
++
++ ss->busclk = devm_clk_get(&pdev->dev, "ahb");
++ if (IS_ERR(ss->busclk)) {
++ err = PTR_ERR(ss->busclk);
++ dev_err(&pdev->dev, "Cannot get AHB SS clock err=%d\n", err);
++ return err;
++ }
++ dev_dbg(&pdev->dev, "clock ahb_ss acquired\n");
++
++ /* Enable both clocks */
++ err = clk_prepare_enable(ss->busclk);
++ if (err != 0) {
++ dev_err(&pdev->dev, "Cannot prepare_enable busclk\n");
++ return err;
++ }
++ err = clk_prepare_enable(ss->ssclk);
++ if (err != 0) {
++ dev_err(&pdev->dev, "Cannot prepare_enable ssclk\n");
++ clk_disable_unprepare(ss->busclk);
++ return err;
++ }
++
++ /*
++ * Check that clock have the correct rates gived in the datasheet
++ * Try to set the clock to the maximum allowed
++ */
++ err = clk_set_rate(ss->ssclk, cr_mod);
++ if (err != 0) {
++ dev_err(&pdev->dev, "Cannot set clock rate to ssclk\n");
++ clk_disable_unprepare(ss->ssclk);
++ clk_disable_unprepare(ss->busclk);
++ return err;
++ }
++
++ cr = clk_get_rate(ss->busclk);
++ if (cr >= cr_ahb)
++ dev_dbg(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
++ cr, cr / 1000000, cr_ahb);
++ else
++ dev_warn(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
++ cr, cr / 1000000, cr_ahb);
++
++ cr = clk_get_rate(ss->ssclk);
++ if (cr <= cr_mod)
++ if (cr < cr_mod)
++ dev_info(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n",
++ cr, cr / 1000000, cr_mod);
++ else
++ dev_dbg(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n",
++ cr, cr / 1000000, cr_mod);
++ else
++ dev_warn(&pdev->dev, "Clock ss is at %lu (%lu MHz) (must be <= %lu)\n",
++ cr, cr / 1000000, cr_mod);
++
++ /*
++ * Datasheet named it "Die Bonding ID"
++ * I expect to be a sort of Security System Revision number.
++ * Since the A80 seems to have an other version of SS
++ * this info could be useful
++ */
++ writel(SS_ENABLED, ss->base + SS_CTL);
++ v = readl(ss->base + SS_CTL);
++ v >>= 16;
++ v &= 0x07;
++ dev_info(&pdev->dev, "Die ID %d\n", v);
++ writel(0, ss->base + SS_CTL);
++
++ ss->dev = &pdev->dev;
++
++ mutex_init(&ss->lock);
++ mutex_init(&ss->bufin_lock);
++ mutex_init(&ss->bufout_lock);
++
++ err = crypto_register_ahash(&sunxi_md5_alg);
++ if (err)
++ goto error_md5;
++ err = crypto_register_ahash(&sunxi_sha1_alg);
++ if (err)
++ goto error_sha1;
++ err = crypto_register_algs(sunxi_cipher_algs,
++ ARRAY_SIZE(sunxi_cipher_algs));
++ if (err)
++ goto error_ciphers;
++
++ return 0;
++error_ciphers:
++ crypto_unregister_ahash(&sunxi_sha1_alg);
++error_sha1:
++ crypto_unregister_ahash(&sunxi_md5_alg);
++error_md5:
++ clk_disable_unprepare(ss->ssclk);
++ clk_disable_unprepare(ss->busclk);
++ return err;
++}
++
++static int __exit sunxi_ss_remove(struct platform_device *pdev)
++{
++ if (!pdev->dev.of_node)
++ return 0;
++
++ crypto_unregister_ahash(&sunxi_md5_alg);
++ crypto_unregister_ahash(&sunxi_sha1_alg);
++ crypto_unregister_algs(sunxi_cipher_algs,
++ ARRAY_SIZE(sunxi_cipher_algs));
++
++ if (ss->buf_in != NULL)
++ kfree(ss->buf_in);
++ if (ss->buf_out != NULL)
++ kfree(ss->buf_out);
++
++ writel(0, ss->base + SS_CTL);
++ clk_disable_unprepare(ss->busclk);
++ clk_disable_unprepare(ss->ssclk);
++ return 0;
++}
++
++static const struct of_device_id a20ss_crypto_of_match_table[] = {
++ { .compatible = "allwinner,sun7i-a20-crypto" },
++ {}
++};
++MODULE_DEVICE_TABLE(of, a20ss_crypto_of_match_table);
++
++static struct platform_driver sunxi_ss_driver = {
++ .probe = sunxi_ss_probe,
++ .remove = __exit_p(sunxi_ss_remove),
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "sunxi-ss",
++ .of_match_table = a20ss_crypto_of_match_table,
++ },
++};
++
++module_platform_driver(sunxi_ss_driver);
++
++MODULE_DESCRIPTION("Allwinner Security System cryptographic accelerator");
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Corentin LABBE <clabbe.montjoie@gmail.com>");
+Index: linux-4.1.3/drivers/crypto/sunxi-ss/sunxi-ss-hash.c
+===================================================================
+--- /dev/null
++++ linux-4.1.3/drivers/crypto/sunxi-ss/sunxi-ss-hash.c
+@@ -0,0 +1,445 @@
++/*
++ * sunxi-ss-hash.c - hardware cryptographic accelerator for Allwinner A20 SoC
++ *
++ * Copyright (C) 2013-2014 Corentin LABBE <clabbe.montjoie@gmail.com>
++ *
++ * This file add support for MD5 and SHA1.
++ *
++ * You could find the datasheet in Documentation/arm/sunxi/README
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++#include "sunxi-ss.h"
++
++/* This is a totaly arbitrary value */
++#define SS_TIMEOUT 100
++
++extern struct sunxi_ss_ctx *ss;
++
++int sunxi_hash_crainit(struct crypto_tfm *tfm)
++{
++ crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
++ sizeof(struct sunxi_req_ctx));
++ return 0;
++}
++
++/* sunxi_hash_init: initialize request context */
++int sunxi_hash_init(struct ahash_request *areq)
++{
++ const char *hash_type;
++ struct sunxi_req_ctx *op = ahash_request_ctx(areq);
++
++ memset(op, 0, sizeof(struct sunxi_req_ctx));
++
++ hash_type = crypto_tfm_alg_name(areq->base.tfm);
++
++ if (strcmp(hash_type, "sha1") == 0)
++ op->mode = SS_OP_SHA1;
++ if (strcmp(hash_type, "md5") == 0)
++ op->mode = SS_OP_MD5;
++ if (op->mode == 0)
++ return -EINVAL;
++
++ return 0;
++}
++
++static u32 rx_cnt;
++
++inline void ss_writer(const u32 v)
++{
++ u32 spaces;
++
++ writel(v, ss->base + SS_RXFIFO);
++ rx_cnt--;
++ while (rx_cnt == 0) {
++ spaces = readl_relaxed(ss->base + SS_FCSR);
++ rx_cnt = SS_RXFIFO_SPACES(spaces);
++ }
++}
++
++inline void ss_writer_relaxed(const u32 v)
++{
++ u32 spaces;
++
++ writel_relaxed(v, ss->base + SS_RXFIFO);
++ rx_cnt--;
++ while (rx_cnt == 0) {
++ spaces = readl_relaxed(ss->base + SS_FCSR);
++ rx_cnt = SS_RXFIFO_SPACES(spaces);
++ }
++}
++
++/*
++ * sunxi_hash_update: update hash engine
++ *
++ * Could be used for both SHA1 and MD5
++ * Write data by step of 32bits and put then in the SS.
++ *
++ * Since we cannot leave partial data and hash state in the engine,
++ * we need to get the hash state at the end of this function.
++ * After some work, I have found that we can get the hash state every 64o
++ *
++ * So the first work is to get the number of bytes to write to SS modulo 64
++ * The extra bytes will go to two different destination:
++ * op->wait for full 32bits word
++ * op->wb (waiting bytes) for partial 32 bits word
++ * So we can have up to (64/4)-1 op->wait words and 0/1/2/3 bytes in wb
++ *
++ * So at the begin of update()
++ * if op->nwait * 4 + areq->nbytes < 64
++ * => all data writed to wait buffers and end=0
++ * if not write all nwait to the device and position end to complete to 64o
++ *
++ * example 1:
++ * update1 60o => nwait=15
++ * update2 60o => need one more word to have 64o
++ * end=4
++ * so write all data in op->wait and one word of SGs
++ * write remaining data in op->wait
++ * final state op->nwait=14
++ */
++int sunxi_hash_update(struct ahash_request *areq)
++{
++ u32 v, ivmode = 0;
++ unsigned int i = 0;
++ /*
++ * i is the total bytes read from SGs, to be compared to areq->nbytes
++ * i is important because we cannot rely on SG length since the sum of
++ * SG->length could be greater than areq->nbytes
++ */
++
++ struct sunxi_req_ctx *op = ahash_request_ctx(areq);
++ struct scatterlist *in_sg;
++ unsigned int in_i = 0; /* advancement in the current SG */
++ u64 end;
++ /*
++ * end is the position when we need to stop writing to the device,
++ * to be compared to i
++ */
++ int in_r;
++ void *src_addr;
++
++ dev_dbg(ss->dev, "%s %s bc=%llu len=%u mode=%x bw=%u ww=%u",
++ __func__, crypto_tfm_alg_name(areq->base.tfm),
++ op->byte_count, areq->nbytes, op->mode,
++ op->nbw, op->nwait);
++
++ if (areq->nbytes == 0)
++ return 0;
++
++ end = ((areq->nbytes + op->nwait * 4 + op->nbw) / 64) * 64
++ - op->nbw - op->nwait * 4;
++
++ if (end > areq->nbytes || areq->nbytes - end > 63) {
++ dev_err(ss->dev, "ERROR: Bound error %llu %u\n",
++ end, areq->nbytes);
++ return -EINVAL;
++ }
++
++ if (op->nwait > 0 && end > 0) {
++ /* a precedent update was done */
++ for (i = 0; i < op->nwait; i++) {
++ ss_writer(op->wait[i]);
++ op->byte_count += 4;
++ }
++ op->nwait = 0;
++ }
++
++ mutex_lock(&ss->lock);
++ /*
++ * if some data have been processed before,
++ * we need to restore the partial hash state
++ */
++ if (op->byte_count > 0) {
++ ivmode = SS_IV_ARBITRARY;
++ for (i = 0; i < 5; i++)
++ writel(op->hash[i], ss->base + SS_IV0 + i * 4);
++ }
++ /* Enable the device */
++ writel(op->mode | SS_ENABLED | ivmode, ss->base + SS_CTL);
++
++ rx_cnt = 0;
++ i = 0;
++
++ in_sg = areq->src;
++ src_addr = kmap(sg_page(in_sg)) + in_sg->offset;
++ if (src_addr == NULL) {
++ mutex_unlock(&ss->lock);
++ dev_err(ss->dev, "ERROR: Cannot kmap source buffer\n");
++ return -EFAULT;
++ }
++ do {
++ /*
++ * step 1, if some bytes remains from last SG,
++ * try to complete them to 4 and send that word
++ */
++ if (op->nbw > 0) {
++ while (op->nbw < 4 && i < areq->nbytes &&
++ in_i < in_sg->length) {
++ op->wb |= (*(u8 *)(src_addr + in_i))
++ << (8 * op->nbw);
++ dev_dbg(ss->dev, "%s Complete w=%d wb=%x\n",
++ __func__, op->nbw, op->wb);
++ i++;
++ in_i++;
++ op->nbw++;
++ }
++ if (op->nbw == 4) {
++ if (i <= end) {
++ ss_writer(op->wb);
++ op->byte_count += 4;
++ } else {
++ op->wait[op->nwait] = op->wb;
++ op->nwait++;
++ dev_dbg(ss->dev, "%s Keep %u bytes after %llu\n",
++ __func__, op->nwait, end);
++ }
++ op->nbw = 0;
++ op->wb = 0;
++ }
++ }
++ /* step 2, main loop, read data 4bytes at a time */
++ while (i < areq->nbytes && in_i < in_sg->length) {
++ /* how many bytes we can read, (we need 4) */
++ in_r = min(in_sg->length - in_i, areq->nbytes - i);
++ if (in_r < 4) {
++ /* Not enough data to write to the device */
++ op->wb = 0;
++ while (in_r > 0) {
++ op->wb |= (*(u8 *)(src_addr + in_i))
++ << (8 * op->nbw);
++ dev_dbg(ss->dev, "%s ending bw=%d wb=%x\n",
++ __func__, op->nbw, op->wb);
++ in_r--;
++ i++;
++ in_i++;
++ op->nbw++;
++ }
++ goto nextsg;
++ }
++ v = *(u32 *)(src_addr + in_i);
++ if (i < end) {
++ /* last write must be done without relaxed */
++ if (i + 4 >= end)
++ ss_writer(v);
++ else
++ ss_writer_relaxed(v);
++ i += 4;
++ op->byte_count += 4;
++ in_i += 4;
++ } else {
++ op->wait[op->nwait] = v;
++ i += 4;
++ in_i += 4;
++ op->nwait++;
++ dev_dbg(ss->dev, "%s Keep word ww=%u after %llu\n",
++ __func__, op->nwait, end);
++ if (op->nwait > 15) {
++ dev_err(ss->dev, "FATAL: Cannot enqueue more, bug?\n");
++ writel(0, ss->base + SS_CTL);
++ mutex_unlock(&ss->lock);
++ return -EIO;
++ }
++ }
++ }
++nextsg:
++ /* Nothing more to read in this SG */
++ if (in_i == in_sg->length) {
++ kunmap(sg_page(in_sg));
++ do {
++ in_sg = sg_next(in_sg);
++ } while (in_sg != NULL && in_sg->length == 0);
++ in_i = 0;
++ if (in_sg != NULL) {
++ src_addr = kmap(sg_page(in_sg)) + in_sg->offset;
++ if (src_addr == NULL) {
++ mutex_unlock(&ss->lock);
++ dev_err(ss->dev, "ERROR: Cannot kmap source buffer\n");
++ return -EFAULT;
++ }
++ }
++ }
++ } while (in_sg != NULL && i < areq->nbytes);
++
++ /* ask the device to finish the hashing */
++ writel(op->mode | SS_ENABLED | SS_DATA_END, ss->base + SS_CTL);
++ i = 0;
++ do {
++ v = readl(ss->base + SS_CTL);
++ i++;
++ } while (i < SS_TIMEOUT && (v & SS_DATA_END) > 0);
++ if (i >= SS_TIMEOUT) {
++ dev_err(ss->dev, "ERROR: %s hash end timeout after %d loop, CTL=%x\n",
++ __func__, i, v);
++ writel(0, ss->base + SS_CTL);
++ mutex_unlock(&ss->lock);
++ return -EIO;
++ }
++
++ /* get the partial hash */
++ if (op->mode == SS_OP_SHA1) {
++ for (i = 0; i < 5; i++)
++ op->hash[i] = readl(ss->base + SS_MD0 + i * 4);
++ } else {
++ for (i = 0; i < 4; i++)
++ op->hash[i] = readl(ss->base + SS_MD0 + i * 4);
++ }
++
++ writel(0, ss->base + SS_CTL);
++ mutex_unlock(&ss->lock);
++ return 0;
++}
++
++/*
++ * sunxi_hash_final: finalize hashing operation
++ *
++ * If we have some remaining bytes, we write them.
++ * Then ask the SS for finalizing the hashing operation
++ */
++int sunxi_hash_final(struct ahash_request *areq)
++{
++ u32 v, ivmode = 0;
++ unsigned int i;
++ int zeros;
++ unsigned int index, padlen;
++ __be64 bits;
++ struct sunxi_req_ctx *op = ahash_request_ctx(areq);
++
++ dev_dbg(ss->dev, "%s byte=%llu len=%u mode=%x bw=%u %x h=%x ww=%u",
++ __func__, op->byte_count, areq->nbytes, op->mode,
++ op->nbw, op->wb, op->hash[0], op->nwait);
++
++ mutex_lock(&ss->lock);
++ rx_cnt = 0;
++
++ /*
++ * if we have already writed something,
++ * restore the partial hash state
++ */
++ if (op->byte_count > 0) {
++ ivmode = SS_IV_ARBITRARY;
++ for (i = 0; i < 5; i++)
++ writel(op->hash[i], ss->base + SS_IV0 + i * 4);
++ }
++ writel(op->mode | SS_ENABLED | ivmode, ss->base + SS_CTL);
++
++ /* write the remaining words of the wait buffer */
++ if (op->nwait > 0) {
++ for (i = 0; i < op->nwait; i++) {
++ v = op->wait[i];
++ ss_writer(v);
++ op->byte_count += 4;
++ dev_dbg(ss->dev, "%s write %llu i=%u %x\n",
++ __func__, op->byte_count, i, v);
++ }
++ op->nwait = 0;
++ }
++
++ /* write the remaining bytes of the nbw buffer */
++ if (op->nbw > 0) {
++ op->wb |= ((1 << 7) << (op->nbw * 8));
++ ss_writer(op->wb);
++ } else {
++ ss_writer((1 << 7));
++ }
++
++ /*
++ * number of space to pad to obtain 64o minus 8(size) minus 4 (final 1)
++ * I take the operations from other md5/sha1 implementations
++ */
++
++ /* we have already send 4 more byte of which nbw data */
++ if (op->mode == SS_OP_MD5) {
++ index = (op->byte_count + 4) & 0x3f;
++ op->byte_count += op->nbw;
++ if (index > 56)
++ zeros = (120 - index) / 4;
++ else
++ zeros = (56 - index) / 4;
++ } else {
++ op->byte_count += op->nbw;
++ index = op->byte_count & 0x3f;
++ padlen = (index < 56) ? (56 - index) : ((64+56) - index);
++ zeros = (padlen - 1) / 4;
++ }
++ for (i = 0; i < zeros; i++)
++ ss_writer(0);
++
++ /* write the length of data */
++ if (op->mode == SS_OP_SHA1) {
++ bits = cpu_to_be64(op->byte_count << 3);
++ ss_writer(bits & 0xffffffff);
++ ss_writer((bits >> 32) & 0xffffffff);
++ } else {
++ ss_writer((op->byte_count << 3) & 0xffffffff);
++ ss_writer((op->byte_count >> 29) & 0xffffffff);
++ }
++
++ /* Tell the SS to stop the hashing */
++ writel(op->mode | SS_ENABLED | SS_DATA_END, ss->base + SS_CTL);
++
++ /*
++ * Wait for SS to finish the hash.
++ * The timeout could happend only in case of bad overcloking
++ * or driver bug.
++ */
++ i = 0;
++ do {
++ v = readl(ss->base + SS_CTL);
++ i++;
++ } while (i < SS_TIMEOUT && (v & SS_DATA_END) > 0);
++ if (i >= SS_TIMEOUT) {
++ dev_err(ss->dev, "ERROR: hash end timeout %d>%d ctl=%x len=%u\n",
++ i, SS_TIMEOUT, v, areq->nbytes);
++ writel(0, ss->base + SS_CTL);
++ mutex_unlock(&ss->lock);
++ return -EIO;
++ }
++
++ /* Get the hash from the device */
++ if (op->mode == SS_OP_SHA1) {
++ for (i = 0; i < 5; i++) {
++ v = cpu_to_be32(readl(ss->base + SS_MD0 + i * 4));
++ memcpy(areq->result + i * 4, &v, 4);
++ }
++ } else {
++ for (i = 0; i < 4; i++) {
++ v = readl(ss->base + SS_MD0 + i * 4);
++ memcpy(areq->result + i * 4, &v, 4);
++ }
++ }
++ writel(0, ss->base + SS_CTL);
++ mutex_unlock(&ss->lock);
++ return 0;
++}
++
++/* sunxi_hash_finup: finalize hashing operation after an update */
++int sunxi_hash_finup(struct ahash_request *areq)
++{
++ int err;
++
++ err = sunxi_hash_update(areq);
++ if (err != 0)
++ return err;
++
++ return sunxi_hash_final(areq);
++}
++
++/* combo of init/update/final functions */
++int sunxi_hash_digest(struct ahash_request *areq)
++{
++ int err;
++
++ err = sunxi_hash_init(areq);
++ if (err != 0)
++ return err;
++
++ err = sunxi_hash_update(areq);
++ if (err != 0)
++ return err;
++
++ return sunxi_hash_final(areq);
++}
+Index: linux-4.1.3/drivers/crypto/sunxi-ss/sunxi-ss.h
+===================================================================
+--- /dev/null
++++ linux-4.1.3/drivers/crypto/sunxi-ss/sunxi-ss.h
+@@ -0,0 +1,193 @@
++/*
++ * sunxi-ss.c - hardware cryptographic accelerator for Allwinner A20 SoC
++ *
++ * Copyright (C) 2013-2014 Corentin LABBE <clabbe.montjoie@gmail.com>
++ *
++ * Support AES cipher with 128,192,256 bits keysize.
++ * Support MD5 and SHA1 hash algorithms.
++ * Support DES and 3DES
++ *
++ * You could find the datasheet in Documentation/arm/sunxi/README
++ *
++ * Licensed under the GPL-2.
++ */
++
++#include <linux/clk.h>
++#include <linux/crypto.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <crypto/scatterwalk.h>
++#include <linux/scatterlist.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <crypto/md5.h>
++#include <crypto/sha.h>
++#include <crypto/hash.h>
++#include <crypto/internal/hash.h>
++#include <crypto/aes.h>
++#include <crypto/des.h>
++#include <crypto/internal/rng.h>
++
++#define SS_CTL 0x00
++#define SS_KEY0 0x04
++#define SS_KEY1 0x08
++#define SS_KEY2 0x0C
++#define SS_KEY3 0x10
++#define SS_KEY4 0x14
++#define SS_KEY5 0x18
++#define SS_KEY6 0x1C
++#define SS_KEY7 0x20
++
++#define SS_IV0 0x24
++#define SS_IV1 0x28
++#define SS_IV2 0x2C
++#define SS_IV3 0x30
++
++#define SS_CNT0 0x34
++#define SS_CNT1 0x38
++#define SS_CNT2 0x3C
++#define SS_CNT3 0x40
++
++#define SS_FCSR 0x44
++#define SS_ICSR 0x48
++
++#define SS_MD0 0x4C
++#define SS_MD1 0x50
++#define SS_MD2 0x54
++#define SS_MD3 0x58
++#define SS_MD4 0x5C
++
++#define SS_RXFIFO 0x200
++#define SS_TXFIFO 0x204
++
++/* SS_CTL configuration values */
++
++/* PRNG generator mode - bit 15 */
++#define SS_PRNG_ONESHOT (0 << 15)
++#define SS_PRNG_CONTINUE (1 << 15)
++
++/* IV mode for hash */
++#define SS_IV_ARBITRARY (1 << 14)
++
++/* SS operation mode - bits 12-13 */
++#define SS_ECB (0 << 12)
++#define SS_CBC (1 << 12)
++#define SS_CNT (2 << 12)
++
++/* Counter width for CNT mode - bits 10-11 */
++#define SS_CNT_16BITS (0 << 10)
++#define SS_CNT_32BITS (1 << 10)
++#define SS_CNT_64BITS (2 << 10)
++
++/* Key size for AES - bits 8-9 */
++#define SS_AES_128BITS (0 << 8)
++#define SS_AES_192BITS (1 << 8)
++#define SS_AES_256BITS (2 << 8)
++
++/* Operation direction - bit 7 */
++#define SS_ENCRYPTION (0 << 7)
++#define SS_DECRYPTION (1 << 7)
++
++/* SS Method - bits 4-6 */
++#define SS_OP_AES (0 << 4)
++#define SS_OP_DES (1 << 4)
++#define SS_OP_3DES (2 << 4)
++#define SS_OP_SHA1 (3 << 4)
++#define SS_OP_MD5 (4 << 4)
++#define SS_OP_PRNG (5 << 4)
++
++/* Data end bit - bit 2 */
++#define SS_DATA_END (1 << 2)
++
++/* PRNG start bit - bit 1 */
++#define SS_PRNG_START (1 << 1)
++
++/* SS Enable bit - bit 0 */
++#define SS_DISABLED (0 << 0)
++#define SS_ENABLED (1 << 0)
++
++/* SS_FCSR configuration values */
++/* RX FIFO status - bit 30 */
++#define SS_RXFIFO_FREE (1 << 30)
++
++/* RX FIFO empty spaces - bits 24-29 */
++#define SS_RXFIFO_SPACES(val) (((val) >> 24) & 0x3f)
++
++/* TX FIFO status - bit 22 */
++#define SS_TXFIFO_AVAILABLE (1 << 22)
++
++/* TX FIFO available spaces - bits 16-21 */
++#define SS_TXFIFO_SPACES(val) (((val) >> 16) & 0x3f)
++
++#define SS_RXFIFO_EMP_INT_PENDING (1 << 10)
++#define SS_TXFIFO_AVA_INT_PENDING (1 << 8)
++#define SS_RXFIFO_EMP_INT_ENABLE (1 << 2)
++#define SS_TXFIFO_AVA_INT_ENABLE (1 << 0)
++
++/* SS_ICSR configuration values */
++#define SS_ICS_DRQ_ENABLE (1 << 4)
++
++struct sunxi_ss_ctx {
++ void __iomem *base;
++ int irq;
++ struct clk *busclk;
++ struct clk *ssclk;
++ struct device *dev;
++ struct resource *res;
++ void *buf_in; /* pointer to data to be uploaded to the device */
++ size_t buf_in_size; /* size of buf_in */
++ void *buf_out;
++ size_t buf_out_size;
++ struct mutex lock; /* control the use of the device */
++ struct mutex bufout_lock; /* control the use of buf_out*/
++ struct mutex bufin_lock; /* control the sue of buf_in*/
++};
++
++struct sunxi_tfm_ctx {
++ u32 key[AES_MAX_KEY_SIZE / 4];/* divided by sizeof(u32) */
++ u32 keylen;
++ u32 keymode;
++};
++
++struct sunxi_req_ctx {
++ u32 mode;
++ u64 byte_count; /* number of bytes "uploaded" to the device */
++ u32 wb; /* a partial word waiting to be completed and
++ uploaded to the device */
++ /* number of bytes to be uploaded in the wb word */
++ unsigned int nbw;
++ u32 hash[5];
++ u32 wait[64];
++ unsigned int nwait;
++};
++
++#define SS_SEED_LEN (192/8)
++#define SS_DATA_LEN (160/8)
++
++struct prng_context {
++ u32 seed[SS_SEED_LEN/4];
++ unsigned int slen;
++};
++
++int sunxi_hash_crainit(struct crypto_tfm *tfm);
++int sunxi_hash_init(struct ahash_request *areq);
++int sunxi_hash_update(struct ahash_request *areq);
++int sunxi_hash_final(struct ahash_request *areq);
++int sunxi_hash_finup(struct ahash_request *areq);
++int sunxi_hash_digest(struct ahash_request *areq);
++int sunxi_hash_export(struct ahash_request *areq, void *out);
++int sunxi_hash_import(struct ahash_request *areq, const void *in);
++
++int sunxi_ss_aes_poll(struct ablkcipher_request *areq, u32 mode);
++int sunxi_ss_des_poll(struct ablkcipher_request *areq, u32 mode);
++int sunxi_ss_cipher_init(struct crypto_tfm *tfm);
++int sunxi_ss_cipher_encrypt(struct ablkcipher_request *areq);
++int sunxi_ss_cipher_decrypt(struct ablkcipher_request *areq);
++int sunxi_ss_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
++ unsigned int keylen);
++int sunxi_ss_des_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
++ unsigned int keylen);
++int sunxi_ss_des3_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
++ unsigned int keylen);
new file mode 100644
@@ -0,0 +1,252 @@
+Index: linux-4.1.3/arch/arm/boot/dts/Makefile
+===================================================================
+--- linux-4.1.3.orig/arch/arm/boot/dts/Makefile
++++ linux-4.1.3/arch/arm/boot/dts/Makefile
+@@ -554,6 +554,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
+ sun7i-a20-cubietruck.dtb \
+ sun7i-a20-hummingbird.dtb \
+ sun7i-a20-i12-tvbox.dtb \
++ sun7i-a20-lamobo-r1.dtb \
+ sun7i-a20-m3.dtb \
+ sun7i-a20-olinuxino-lime.dtb \
+ sun7i-a20-olinuxino-lime2.dtb \
+Index: linux-4.1.3/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
+===================================================================
+--- /dev/null
++++ linux-4.1.3/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
+@@ -0,0 +1,235 @@
++/*
++ * Copyright 2015 Daniel Golle <daniel@makrotopia.org>
++ * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This library is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License, or (at your option) any later version.
++ *
++ * This library is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public
++ * License along with this library; if not, write to the Free
++ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
++ * MA 02110-1301 USA
++ *
++ * Or, alternatively,
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/dts-v1/;
++#include "sun7i-a20.dtsi"
++#include "sunxi-common-regulators.dtsi"
++#include <dt-bindings/input/input.h>
++
++/ {
++ model = "Lamobo R1";
++ compatible = "lamobo,lamobo-r1", "allwinner,sun7i-a20";
++
++ soc@01c00000 {
++ spi0: spi@01c05000 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi0_pins_a>;
++ status = "okay";
++ };
++
++ mmc0: mmc@01c0f000 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_lamobo>;
++ vmmc-supply = <®_vcc3v3>;
++ bus-width = <4>;
++ cd-gpios = <&pio 7 10 0>; /* PH10 */
++ cd-inverted;
++ status = "okay";
++ };
++
++ usbphy: phy@01c13400 {
++ usb1_vbus-supply = <®_usb1_vbus>;
++ usb2_vbus-supply = <®_usb2_vbus>;
++ status = "okay";
++ };
++
++ ehci0: usb@01c14000 {
++ status = "okay";
++ };
++
++ ohci0: usb@01c14400 {
++ status = "okay";
++ };
++
++ ahci: sata@01c18000 {
++ target-supply = <®_ahci_5v>;
++ status = "okay";
++ };
++
++ ehci1: usb@01c1c000 {
++ status = "okay";
++ };
++
++ ohci1: usb@01c1c400 {
++ status = "okay";
++ };
++
++ pinctrl@01c20800 {
++ mmc0_cd_pin_lamobo: mmc0_cd_pin@0 {
++ allwinner,pins = "PH10";
++ allwinner,function = "gpio_in";
++ allwinner,drive = <0>;
++ allwinner,pull = <1>;
++ };
++
++ gmac_power_pin_lamobo: gmac_power_pin@0 {
++ allwinner,pins = "PH23";
++ allwinner,function = "gpio_out";
++ allwinner,drive = <0>;
++ allwinner,pull = <0>;
++ };
++
++ led_pins_lamobo: led_pins@0 {
++ allwinner,pins = "PH2";
++ allwinner,function = "gpio_out";
++ allwinner,drive = <1>;
++ allwinner,pull = <0>;
++ };
++ };
++
++ lradc: lradc@01c22800 {
++ allwinner,chan0-step = <200>;
++ linux,chan0-keycodes = <KEY_VOLUMEUP KEY_VOLUMEDOWN
++ KEY_MENU KEY_SEARCH KEY_HOME
++ KEY_ESC KEY_ENTER>;
++ status = "okay";
++ };
++
++ ir0: ir@01c21800 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&ir0_pins_a>;
++ status = "okay";
++ };
++
++ uart0: serial@01c28000 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart0_pins_a>;
++ status = "okay";
++ };
++
++ uart3: serial@01c28c00 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart3_pins_b>;
++ status = "okay";
++ };
++
++ uart7: serial@01c29c00 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart7_pins_a>;
++ status = "okay";
++ };
++
++ i2c0: i2c@01c2ac00 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c0_pins_a>;
++ status = "okay";
++
++ axp209: pmic@34 {
++ compatible = "x-powers,axp209";
++ reg = <0x34>;
++ interrupt-parent = <&nmi_intc>;
++ interrupts = <0 8>;
++
++ interrupt-controller;
++ #interrupt-cells = <1>;
++ };
++ };
++
++ i2c1: i2c@01c2b000 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c1_pins_a>;
++ status = "okay";
++ };
++
++ i2c2: i2c@01c2b400 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c2_pins_a>;
++ status = "okay";
++ };
++
++ gmac: ethernet@01c50000 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&gmac_pins_rgmii_a>;
++ phy = <&phy1>;
++ phy-mode = "rgmii";
++ phy-supply = <®_gmac_3v3>;
++ status = "okay";
++
++ phy1: ethernet-phy@1 {
++ reg = <1>;
++ };
++ };
++ };
++
++ leds {
++ compatible = "gpio-leds";
++ pinctrl-names = "default";
++ pinctrl-0 = <&led_pins_lamobo>;
++
++ green {
++ label = "lamobo:green:usr";
++ gpios = <&pio 7 24 0>;
++ default-state = "on";
++ };
++ };
++
++ reg_ahci_5v: ahci-5v {
++ status = "okay";
++ };
++
++ reg_usb1_vbus: usb1-vbus {
++ status = "okay";
++ };
++
++ reg_usb2_vbus: usb2-vbus {
++ status = "okay";
++ };
++
++ reg_gmac_3v3: gmac-3v3 {
++ compatible = "regulator-fixed";
++ pinctrl-names = "default";
++ pinctrl-0 = <&gmac_power_pin_lamobo>;
++ regulator-name = "gmac-3v3";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ startup-delay-us = <100000>;
++ enable-active-high;
++ gpio = <&pio 7 23 0>;
++ status = "okay";
++ };
++};
Similar to brcm2708 have framebuffer video support built-in so fbconsole gets initialized during boot. Plus more kernel config carefully sync'ed against upstream sunxi_defconfig. Signed-off-by: Daniel Golle <daniel@makrotopia.org> --- target/linux/sunxi/config-4.1 | 599 ++++++++ ...201-dt-sun7i-add-oob-irq-to-bcm-sdio-wifi.patch | 68 + .../202-dt-sun7i-add-bluetooth-to-cubietruck.patch | 77 + .../patches-4.1/270-dt-sun7i-add-ss-to-a20.patch | 19 + .../sunxi/patches-4.1/271-crypto-add-ss.patch | 1508 ++++++++++++++++++++ .../patches-4.1/302-dt-sun7i-add-lamobo-r1.patch | 252 ++++ 6 files changed, 2523 insertions(+) create mode 100644 target/linux/sunxi/config-4.1 create mode 100644 target/linux/sunxi/patches-4.1/201-dt-sun7i-add-oob-irq-to-bcm-sdio-wifi.patch create mode 100644 target/linux/sunxi/patches-4.1/202-dt-sun7i-add-bluetooth-to-cubietruck.patch create mode 100644 target/linux/sunxi/patches-4.1/270-dt-sun7i-add-ss-to-a20.patch create mode 100644 target/linux/sunxi/patches-4.1/271-crypto-add-ss.patch create mode 100644 target/linux/sunxi/patches-4.1/302-dt-sun7i-add-lamobo-r1.patch