From patchwork Mon Dec 14 03:04:28 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikolay Martynov X-Patchwork-Id: 556278 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from arrakis.dune.hu (arrakis.dune.hu [78.24.191.176]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id EB9D11402A1 for ; Mon, 14 Dec 2015 14:07:28 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=jkf44Uv9; dkim-atps=neutral Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id D614A28443D; Mon, 14 Dec 2015 04:05:33 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on arrakis.dune.hu X-Spam-Level: X-Spam-Status: No, score=-1.5 required=5.0 tests=BAYES_00,FREEMAIL_FROM, T_DKIM_INVALID autolearn=unavailable version=3.3.2 Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id 0B7D4283F62 for ; Mon, 14 Dec 2015 04:05:08 +0100 (CET) X-policyd-weight: using cached result; rate: -8.5 Received: from mail-io0-f182.google.com (mail-io0-f182.google.com [209.85.223.182]) by arrakis.dune.hu (Postfix) with ESMTPS for ; Mon, 14 Dec 2015 04:05:05 +0100 (CET) Received: by iofo67 with SMTP id o67so30095577iof.3 for ; Sun, 13 Dec 2015 19:05:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8RA/thiyeXJtZPIEKKN2CsJw8db9QJeavM5j3NbgRN8=; b=jkf44Uv9rJSwGcmubQCNB6RiRKMt57aeBCs+1e7VBEwJao/dqloSMX7pu4zoUH4LI2 ySSn6i1kqI2pqA/lMrGbQzoZIOkucUbhKjOTt29LiwvHIpKfAZS5xBTDey9TkC5sH4PU EvjA5HO8c4MaoGC+sjF6MYQC77rmeZAIihF9Gd2O/qq0mUoX+SMgJBjmUKY77LbEwGh1 5fonAKVZlx+I6HBwRVOveBuXb0e3/TbC+LEUlEEhweus2AWkwq0JKqdrxy18ZdUx4zM0 kh6bHUq9yefkTD6ADoJ6ZJBcXKc2wWySO0+ZwOqmh6fZWRc/tsomiw+muyCBb2UmFR5i TngQ== X-Received: by 10.107.131.40 with SMTP id f40mr26618232iod.189.1450062317202; Sun, 13 Dec 2015 19:05:17 -0800 (PST) Received: from kolya-laptop.shuttercorp.net (dhcp-108-170-142-183.cable.user.start.ca. [108.170.142.183]) by smtp.gmail.com with ESMTPSA id e5sm3470402ioj.40.2015.12.13.19.05.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 13 Dec 2015 19:05:16 -0800 (PST) From: Nikolay Martynov To: openwrt-devel@lists.openwrt.org Date: Sun, 13 Dec 2015 22:04:28 -0500 Message-Id: <1450062272-7026-2-git-send-email-mar.kolya@gmail.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1450062272-7026-1-git-send-email-mar.kolya@gmail.com> References: <1450062272-7026-1-git-send-email-mar.kolya@gmail.com> Subject: [OpenWrt-Devel] [PATCH 2/6] ramips: mt7621: setup memory region for pcie controller memory X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: openwrt-devel-bounces@lists.openwrt.org Sender: "openwrt-devel" Only compile tested since I do not have any hardware with devices on pcie bus. Signed-off-by: Nikolay Martynov --- .../0061-mt7621-set-up-pci-memory-region.patch | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 target/linux/ramips/patches-4.3/0061-mt7621-set-up-pci-memory-region.patch diff --git a/target/linux/ramips/patches-4.3/0061-mt7621-set-up-pci-memory-region.patch b/target/linux/ramips/patches-4.3/0061-mt7621-set-up-pci-memory-region.patch new file mode 100644 index 0000000..e6338a9 --- /dev/null +++ b/target/linux/ramips/patches-4.3/0061-mt7621-set-up-pci-memory-region.patch @@ -0,0 +1,42 @@ +--- a/arch/mips/pci/pci-mt7621.c ++++ b/arch/mips/pci/pci-mt7621.c +@@ -46,6 +46,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -553,6 +554,23 @@ set_phy_for_ssc(void) + #endif + } + ++void setup_cm_memory_region(struct resource *mem_resource) ++{ ++ resource_size_t mask; ++ if (mips_cm_numiocu()) { ++ /* FIXME: hardware doesn't accept mask values with 1s after ++ 0s (e.g. 0xffef), so it would be great to warn if that's ++ about to happen */ ++ mask = ~(mem_resource->end - mem_resource->start); ++ ++ write_gcr_reg1_base(mem_resource->start); ++ write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0); ++ printk("PCI coherence region base: 0x%08lx, mask/settings: 0x%08lx\n", ++ read_gcr_reg1_base(), ++ read_gcr_reg1_mask()); ++ } ++} ++ + static int mt7621_pci_probe(struct platform_device *pdev) + { + unsigned long val = 0; +@@ -780,6 +798,7 @@ pcie(2/1/0) link status pcie2_num pcie1_ + } + + pci_load_of_ranges(&mt7621_controller, pdev->dev.of_node); ++ setup_cm_memory_region(mt7621_controller.mem_resource); + register_pci_controller(&mt7621_controller); + return 0; +