From patchwork Fri Dec 11 04:01:38 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikolay Martynov X-Patchwork-Id: 555485 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from arrakis.dune.hu (arrakis.dune.hu [78.24.191.176]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id ADC771402D8 for ; Fri, 11 Dec 2015 15:08:00 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=OvKyrpB2; dkim-atps=neutral Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id 60C46284233; Fri, 11 Dec 2015 05:04:38 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on arrakis.dune.hu X-Spam-Level: X-Spam-Status: No, score=-1.5 required=5.0 tests=BAYES_00,FREEMAIL_FROM, T_DKIM_INVALID autolearn=unavailable version=3.3.2 Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id D8DBE283C2A for ; Fri, 11 Dec 2015 05:02:35 +0100 (CET) X-policyd-weight: using cached result; rate:hard: -8.5 Received: from mail-ob0-f181.google.com (mail-ob0-f181.google.com [209.85.214.181]) by arrakis.dune.hu (Postfix) with ESMTPS for ; Fri, 11 Dec 2015 05:02:22 +0100 (CET) Received: by obbsd4 with SMTP id sd4so24821916obb.0 for ; Thu, 10 Dec 2015 20:02:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gZmnES4kiUcUkbPeKDqoefd9Hl3DARdjRtBDzsrm/sc=; b=OvKyrpB22ECBA1cpf/WHvetx/8E21K9H821Um78szIFsaZN3X/ufz2Rfe72ZJydkuG E/sNSlUYT8gs2QVHTWkEs5fpTIyjl/qAIOLQH8uEiqBQBwVMDlXi5c8oFBL8bLzIcEbU VXaxm40vGscqNJAAY7W7AUHz8F/8CQI7NPlHYF/LFPH5QsvYW4IAf7pf26kRV3D56HWg DCtYAZbWVzjA1Njvdxh+YVV2EULb0XW7kluyU00EpHDYSUXg1MS44V2Ln5Uo9UPi/0iQ GBuqzfAL2DsuTLW0h+EdtGDEy16Y4aCEjPj19anArSIgX4yX6FgHWvwwNjzD9VG6Ogdk IJYA== X-Received: by 10.60.58.166 with SMTP id s6mr12419759oeq.80.1449806552426; Thu, 10 Dec 2015 20:02:32 -0800 (PST) Received: from kolya-laptop.shuttercorp.net (dhcp-108-170-142-183.cable.user.start.ca. [108.170.142.183]) by smtp.gmail.com with ESMTPSA id r82sm7509344oib.10.2015.12.10.20.02.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 10 Dec 2015 20:02:31 -0800 (PST) From: Nikolay Martynov To: blogic@openwrt.org Date: Thu, 10 Dec 2015 23:01:38 -0500 Message-Id: <1449806500-20222-8-git-send-email-mar.kolya@gmail.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1449806500-20222-1-git-send-email-mar.kolya@gmail.com> References: <1449806500-20222-1-git-send-email-mar.kolya@gmail.com> Cc: openwrt-devel@lists.openwrt.org Subject: [OpenWrt-Devel] [PATCH 7/9] ramips: enable CPS for mt7621 X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: openwrt-devel-bounces@lists.openwrt.org Sender: "openwrt-devel" Enables CPS multiprocessing instead ob obsoleted CMP for mt7621. This patch fixes a few issues currently existing on 4.3 kernel with at least ubnt-erx: * iperf shows only 50Mbits on direct gigabit connection to desktop, * ping times jump to 5-6ms to dorectly connected desktop * /proc/interrupts shows spurious interrups (ERR) Signed-off-by: Nikolay Martynov --- target/linux/ramips/dts/mt7621.dtsi | 2 +- target/linux/ramips/mt7621/config-4.3 | 8 +- .../0001-arch-mips-ralink-add-mt7621-support.patch | 134 +++------------------ 3 files changed, 21 insertions(+), 123 deletions(-) diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi index 1f2f5b5..53ac45c 100644 --- a/target/linux/ramips/dts/mt7621.dtsi +++ b/target/linux/ramips/dts/mt7621.dtsi @@ -237,7 +237,7 @@ gic: interrupt-controller@1fbc0000 { compatible = "mti,gic"; - reg = <0x1fbc0000 0x80>; + reg = <0x1fbc0000 0x2000>; interrupt-controller; #interrupt-cells = <3>; diff --git a/target/linux/ramips/mt7621/config-4.3 b/target/linux/ramips/mt7621/config-4.3 index 3657460..f25850a 100644 --- a/target/linux/ramips/mt7621/config-4.3 +++ b/target/linux/ramips/mt7621/config-4.3 @@ -5,10 +5,12 @@ CONFIG_ARCH_HAS_ELF_RANDOMIZE=y # CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set CONFIG_ARCH_HAS_RESET_CONTROLLER=y # CONFIG_ARCH_HAS_SG_CHAIN is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y CONFIG_ARCH_REQUIRE_GPIOLIB=y CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_BOARD_SCACHE=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y @@ -117,7 +119,8 @@ CONFIG_LZO_DECOMPRESS=y CONFIG_MDIO_BOARDINFO=y CONFIG_MIPS=y CONFIG_MIPS_CM=y -CONFIG_MIPS_CMP=y +CONFIG_MIPS_CPC=y +CONFIG_MIPS_CPS=y CONFIG_MIPS_CPU_SCACHE=y CONFIG_MIPS_GIC=y CONFIG_MIPS_GIC_IPI=y @@ -226,9 +229,10 @@ CONFIG_SYS_HAS_CPU_MIPS32_R2=y CONFIG_SYS_HAS_EARLY_PRINTK=y CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_MIPS_CMP=y +CONFIG_SYS_SUPPORTS_MIPS_CPS=y CONFIG_SYS_SUPPORTS_MULTITHREADING=y CONFIG_SYS_SUPPORTS_SCHED_SMT=y CONFIG_SYS_SUPPORTS_SMP=y diff --git a/target/linux/ramips/patches-4.3/0001-arch-mips-ralink-add-mt7621-support.patch b/target/linux/ramips/patches-4.3/0001-arch-mips-ralink-add-mt7621-support.patch index 67d816c..153dd9e 100644 --- a/target/linux/ramips/patches-4.3/0001-arch-mips-ralink-add-mt7621-support.patch +++ b/target/linux/ramips/patches-4.3/0001-arch-mips-ralink-add-mt7621-support.patch @@ -120,7 +120,7 @@ Signed-off-by: John Crispin choice prompt "Ralink SoC selection" default SOC_RT305X -@@ -34,6 +39,15 @@ choice +@@ -34,6 +39,14 @@ choice config SOC_MT7620 bool "MT7620/8" @@ -129,14 +129,13 @@ Signed-off-by: John Crispin + select MIPS_CPU_SCACHE + select SYS_SUPPORTS_MULTITHREADING + select SYS_SUPPORTS_SMP -+ select SYS_SUPPORTS_MIPS_CMP ++ select SYS_SUPPORTS_MIPS_CPS + select MIPS_GIC -+ select IRQ_GIC + select HW_HAS_PCI endchoice choice -@@ -65,6 +79,10 @@ choice +@@ -65,6 +78,10 @@ choice depends on SOC_MT7620 select BUILTIN_DTB @@ -149,7 +148,7 @@ Signed-off-by: John Crispin endif --- a/arch/mips/ralink/Makefile +++ b/arch/mips/ralink/Makefile -@@ -6,16 +6,21 @@ +@@ -6,16 +6,20 @@ # Copyright (C) 2009-2011 Gabor Juhos # Copyright (C) 2013 John Crispin @@ -161,8 +160,7 @@ Signed-off-by: John Crispin obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o +obj-$(CONFIG_IRQ_INTC) += irq.o -+obj-$(CONFIG_MIPS_GIC_IPI) += irq-gic.o -+obj-$(CONFIG_MIPS_MT_SMP) += malta-amon.o ++obj-$(CONFIG_MIPS_GIC) += irq-gic.o + obj-$(CONFIG_SOC_RT288X) += rt288x.o obj-$(CONFIG_SOC_RT305X) += rt305x.o @@ -185,136 +183,28 @@ Signed-off-by: John Crispin +cflags-$(CONFIG_SOC_MT7621) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621 --- /dev/null +++ b/arch/mips/ralink/irq-gic.c -@@ -0,0 +1,42 @@ +@@ -0,0 +1,18 @@ +#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include + -+#include -+#include ++#include ++#include + -+#include +#include + -+#include -+ -+extern int __init gic_of_init(struct device_node *node, -+ struct device_node *parent); -+ +unsigned int get_c0_compare_int(void) +{ + return gic_get_c0_compare_int(); +} + -+static struct of_device_id __initdata of_irq_ids[] = { -+ { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init }, -+ { .compatible = "mti,gic", .data = gic_of_init }, -+ {}, -+}; -+ +void __init +arch_init_irq(void) +{ -+ of_irq_init(of_irq_ids); ++ irqchip_init(); +} ---- /dev/null -+++ b/arch/mips/ralink/malta-amon.c -@@ -0,0 +1,81 @@ -+/* -+ * Copyright (C) 2007 MIPS Technologies, Inc. -+ * All rights reserved. -+ -+ * This program is free software; you can distribute it and/or modify it -+ * under the terms of the GNU General Public License (Version 2) as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * for more details. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -+ * -+ * Arbitrary Monitor interface -+ */ -+ -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+int amon_cpu_avail(int cpu) -+{ -+ struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); + -+ if (cpu < 0 || cpu >= NCPULAUNCH) { -+ pr_debug("avail: cpu%d is out of range\n", cpu); -+ return 0; -+ } -+ -+ launch += cpu; -+ if (!(launch->flags & LAUNCH_FREADY)) { -+ pr_debug("avail: cpu%d is not ready\n", cpu); -+ return 0; -+ } -+ if (launch->flags & (LAUNCH_FGO|LAUNCH_FGONE)) { -+ pr_debug("avail: too late.. cpu%d is already gone\n", cpu); -+ return 0; -+ } -+ -+ return 1; -+} -+ -+void amon_cpu_start(int cpu, -+ unsigned long pc, unsigned long sp, -+ unsigned long gp, unsigned long a0) -+{ -+ volatile struct cpulaunch *launch = -+ (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); -+ -+ if (!amon_cpu_avail(cpu)) -+ return; -+ if (cpu == smp_processor_id()) { -+ pr_debug("launch: I am cpu%d!\n", cpu); -+ return; -+ } -+ launch += cpu; -+ -+ pr_debug("launch: starting cpu%d\n", cpu); -+ -+ launch->pc = pc; -+ launch->gp = gp; -+ launch->sp = sp; -+ launch->a0 = a0; -+ -+ smp_wmb(); /* Target must see parameters before go */ -+ launch->flags |= LAUNCH_FGO; -+ smp_wmb(); /* Target must see go before we poll */ -+ -+ while ((launch->flags & LAUNCH_FGONE) == 0) -+ ; -+ smp_rmb(); /* Target will be updating flags soon */ -+ pr_debug("launch: cpu%d gone!\n", cpu); -+} --- /dev/null +++ b/arch/mips/ralink/mt7621.c -@@ -0,0 +1,209 @@ +@@ -0,0 +1,213 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published @@ -432,6 +322,10 @@ Signed-off-by: John Crispin + { 0 } +}; + ++phys_addr_t mips_cpc_default_phys_base() { ++ panic("Cannot detect cpc address"); ++} ++ +void __init ralink_clk_init(void) +{ + int cpu_fdiv = 0;