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[2003:62:5f09:fc04:7d5c:7449:2b09:aa63]) by smtp.googlemail.com with ESMTPSA id pk7sm11635949wjb.2.2015.10.14.11.39.25 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Oct 2015 11:39:26 -0700 (PDT) From: Martin Blumenstingl To: openwrt-devel@lists.openwrt.org Date: Wed, 14 Oct 2015 20:38:36 +0200 Message-Id: <1444847917-20924-2-git-send-email-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.6.1 In-Reply-To: <1444847917-20924-1-git-send-email-martin.blumenstingl@googlemail.com> References: <1444847917-20924-1-git-send-email-martin.blumenstingl@googlemail.com> Subject: [OpenWrt-Devel] [PATCH 1/2] lantiq: Fixed reading the number of RX FIFOs in the SPI driver X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: openwrt-devel-bounces@lists.openwrt.org Sender: "openwrt-devel" Until now the SPI driver used the TX bits for the RX FIFO. This seems uncritical for now since both are equals on my devices (VR9), but this could cause problems on other SoCs. Signed-off-by: Martin Blumenstingl --- .../linux/lantiq/patches-3.18/0033-SPI-MIPS-lantiq-adds-spi-xway.patch | 2 +- .../linux/lantiq/patches-4.1/0033-SPI-MIPS-lantiq-adds-spi-xway.patch | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/linux/lantiq/patches-3.18/0033-SPI-MIPS-lantiq-adds-spi-xway.patch b/target/linux/lantiq/patches-3.18/0033-SPI-MIPS-lantiq-adds-spi-xway.patch index ed00b34..9cc9349 100644 --- a/target/linux/lantiq/patches-3.18/0033-SPI-MIPS-lantiq-adds-spi-xway.patch +++ b/target/linux/lantiq/patches-3.18/0033-SPI-MIPS-lantiq-adds-spi-xway.patch @@ -913,7 +913,7 @@ Signed-off-by: John Crispin + /* Read module capabilities */ + id = ltq_spi_reg_read(hw, LTQ_SPI_ID); + hw->txfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK; -+ hw->rxfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK; ++ hw->rxfs = (id >> LTQ_SPI_ID_RXFS_SHIFT) & LTQ_SPI_ID_RXFS_MASK; + hw->dma_support = (id & LTQ_SPI_ID_CFG) ? 1 : 0; + + ltq_spi_config_mode_set(hw); diff --git a/target/linux/lantiq/patches-4.1/0033-SPI-MIPS-lantiq-adds-spi-xway.patch b/target/linux/lantiq/patches-4.1/0033-SPI-MIPS-lantiq-adds-spi-xway.patch index 13a1d9a..ffcc95e 100644 --- a/target/linux/lantiq/patches-4.1/0033-SPI-MIPS-lantiq-adds-spi-xway.patch +++ b/target/linux/lantiq/patches-4.1/0033-SPI-MIPS-lantiq-adds-spi-xway.patch @@ -927,7 +927,7 @@ Signed-off-by: John Crispin + /* Read module capabilities */ + id = ltq_spi_reg_read(hw, LTQ_SPI_ID); + hw->txfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK; -+ hw->rxfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK; ++ hw->rxfs = (id >> LTQ_SPI_ID_RXFS_SHIFT) & LTQ_SPI_ID_RXFS_MASK; + hw->dma_support = (id & LTQ_SPI_ID_CFG) ? 1 : 0; + + ltq_spi_config_mode_set(hw);