@@ -913,7 +913,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ /* Read module capabilities */
+ id = ltq_spi_reg_read(hw, LTQ_SPI_ID);
+ hw->txfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK;
-+ hw->rxfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK;
++ hw->rxfs = (id >> LTQ_SPI_ID_RXFS_SHIFT) & LTQ_SPI_ID_RXFS_MASK;
+ hw->dma_support = (id & LTQ_SPI_ID_CFG) ? 1 : 0;
+
+ ltq_spi_config_mode_set(hw);
@@ -927,7 +927,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ /* Read module capabilities */
+ id = ltq_spi_reg_read(hw, LTQ_SPI_ID);
+ hw->txfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK;
-+ hw->rxfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK;
++ hw->rxfs = (id >> LTQ_SPI_ID_RXFS_SHIFT) & LTQ_SPI_ID_RXFS_MASK;
+ hw->dma_support = (id & LTQ_SPI_ID_CFG) ? 1 : 0;
+
+ ltq_spi_config_mode_set(hw);
Until now the SPI driver used the TX bits for the RX FIFO. This seems uncritical for now since both are equals on my devices (VR9), but this could cause problems on other SoCs. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> --- .../linux/lantiq/patches-3.18/0033-SPI-MIPS-lantiq-adds-spi-xway.patch | 2 +- .../linux/lantiq/patches-4.1/0033-SPI-MIPS-lantiq-adds-spi-xway.patch | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)