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[2003:62:5f40:8f04:1df1:2819:1241:e220]) by smtp.googlemail.com with ESMTPSA id pu6sm5981127wjc.34.2015.09.08.10.48.50 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 08 Sep 2015 10:48:50 -0700 (PDT) From: Martin Blumenstingl To: openwrt-devel@lists.openwrt.org Date: Tue, 8 Sep 2015 19:48:21 +0200 Message-Id: <1441734501-10330-1-git-send-email-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.5.1 Cc: Geoffrey McRae Subject: [OpenWrt-Devel] [PATCH] lantiq: Use the BAR0 base address in the ath PCI fixup code X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: openwrt-devel-bounces@lists.openwrt.org Sender: "openwrt-devel" Fixes support for AR9287 on TP-Link TD-W8980 and possibly other devices which have an ath wifi chip at a PCI address other than 0xb8000000 (TD-W8980 for example has it's wifi chip at 0xbc000000). Signed-off-by: Geoffrey McRae Signed-off-by: Martin Blumenstingl --- This patch was initially written by Geoffrey McRae but it was never included due to whitespace problems with his patch: https://lists.openwrt.org/pipermail/openwrt-devel/2014-September/028130.html .../0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch | 8 ++++---- .../0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/linux/lantiq/patches-3.18/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch b/target/linux/lantiq/patches-3.18/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch index 094d16c..ec769ccf 100644 --- a/target/linux/lantiq/patches-3.18/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch +++ b/target/linux/lantiq/patches-3.18/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch @@ -431,8 +431,6 @@ Signed-off-by: John Crispin +#include +#include + -+#define LTQ_PCI_MEM_BASE 0x18000000 -+ +struct ath_fixup { + u16 *cal_data; + unsigned slot; @@ -448,6 +446,7 @@ Signed-off-by: John Crispin + u16 cmd; + u32 bar0; + u32 val; ++ u32 base; + unsigned i; + + for (i = 0; i < ath_num_fixups; i++) { @@ -471,14 +470,15 @@ Signed-off-by: John Crispin + + pr_info("pci %s: fixup device configuration\n", pci_name(dev)); + -+ mem = ioremap(LTQ_PCI_MEM_BASE, 0x10000); ++ base = dev->resource[0].start; ++ mem = ioremap(base, 0x10000); + if (!mem) { + pr_err("pci %s: ioremap error\n", pci_name(dev)); + return; + } + + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); -+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, LTQ_PCI_MEM_BASE); ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, base); + pci_read_config_word(dev, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config_word(dev, PCI_COMMAND, cmd); diff --git a/target/linux/lantiq/patches-4.1/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch b/target/linux/lantiq/patches-4.1/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch index 04c2071..72ae1c9 100644 --- a/target/linux/lantiq/patches-4.1/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch +++ b/target/linux/lantiq/patches-4.1/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch @@ -431,8 +431,6 @@ Signed-off-by: John Crispin +#include +#include + -+#define LTQ_PCI_MEM_BASE 0x18000000 -+ +struct ath_fixup { + u16 *cal_data; + unsigned slot; @@ -448,6 +446,7 @@ Signed-off-by: John Crispin + u16 cmd; + u32 bar0; + u32 val; ++ u32 base; + unsigned i; + + for (i = 0; i < ath_num_fixups; i++) { @@ -471,14 +470,15 @@ Signed-off-by: John Crispin + + pr_info("pci %s: fixup device configuration\n", pci_name(dev)); + -+ mem = ioremap(LTQ_PCI_MEM_BASE, 0x10000); ++ base = dev->resource[0].start; ++ mem = ioremap(base, 0x10000); + if (!mem) { + pr_err("pci %s: ioremap error\n", pci_name(dev)); + return; + } + + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); -+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, LTQ_PCI_MEM_BASE); ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, base); + pci_read_config_word(dev, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config_word(dev, PCI_COMMAND, cmd);