From patchwork Wed Jul 29 15:19:04 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sven Eckelmann X-Patchwork-Id: 501745 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from arrakis.dune.hu (arrakis.dune.hu [78.24.191.176]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id A5F4814030B for ; Thu, 30 Jul 2015 01:19:30 +1000 (AEST) Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id 390BF280672; Wed, 29 Jul 2015 17:18:51 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on arrakis.dune.hu X-Spam-Level: X-Spam-Status: No, score=-1.5 required=5.0 tests=BAYES_00, T_RP_MATCHES_RCVD autolearn=unavailable version=3.3.2 Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id 72D8428050F for ; Wed, 29 Jul 2015 17:18:45 +0200 (CEST) X-policyd-weight: using cached result; rate: -7.6 Received: from v3-1039.vlinux.de (narfation.org [79.140.41.39]) by arrakis.dune.hu (Postfix) with ESMTPS for ; Wed, 29 Jul 2015 17:18:45 +0200 (CEST) Received: from sven-desktop.home.narfation.org (x5d84bc99.dyn.telefonica.de [93.132.188.153]) by v3-1039.vlinux.de (Postfix) with ESMTPSA id 1A7CA110102; Wed, 29 Jul 2015 17:19:17 +0200 (CEST) From: Sven Eckelmann To: openwrt-devel@lists.openwrt.org Date: Wed, 29 Jul 2015 17:19:04 +0200 Message-Id: <1438183144-11471-1-git-send-email-sven@open-mesh.com> X-Mailer: git-send-email 2.5.0 Cc: Sven Eckelmann Subject: [OpenWrt-Devel] [PATCH] rampips: Fix pinmux functions for MT7621 X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: openwrt-devel-bounces@lists.openwrt.org Sender: "openwrt-devel" The pinctrl-rt2880 code doesn't support multiple functions with the same name. This will result in incorrect pinmux configuration. The MT7621 uses 2 bit wide configuration of the sdhci, spi, mdio, pcie, wdt, uart2 and uart3. But the code only changed a single bit for uart3, uart2 and mdio. Also the order of uart2 and uart3 group was exchanged. The spi "nand" settings was also reserved only 7 PINs instead of 8 as the spi "spi" setting. Signed-off-by: Sven Eckelmann --- target/linux/ramips/dts/mt7621.dtsi | 14 +++---- .../0012-MIPS-ralink-add-MT7621-support.patch | 45 +++++++++++++++------- 2 files changed, 38 insertions(+), 21 deletions(-) diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi index 53b215f40f10..f09ec3e5b694 100644 --- a/target/linux/ramips/dts/mt7621.dtsi +++ b/target/linux/ramips/dts/mt7621.dtsi @@ -130,31 +130,31 @@ uart1_pins: uart1 { uart1 { ralink,group = "uart1"; - ralink,function = "uart"; + ralink,function = "uart1"; }; }; uart2_pins: uart2 { uart2 { ralink,group = "uart2"; - ralink,function = "uart"; + ralink,function = "uart2"; }; }; uart3_pins: uart3 { uart3 { ralink,group = "uart3"; - ralink,function = "uart"; + ralink,function = "uart3"; }; }; rgmii1_pins: rgmii1 { rgmii1 { ralink,group = "rgmii1"; - ralink,function = "rgmii"; + ralink,function = "rgmii1"; }; }; rgmii2_pins: rgmii2 { rgmii2 { ralink,group = "rgmii2"; - ralink,function = "rgmii"; + ralink,function = "rgmii2"; }; }; mdio_pins: mdio { @@ -172,11 +172,11 @@ nand_pins: nand { spi-nand { ralink,group = "spi"; - ralink,function = "nand"; + ralink,function = "nand1"; }; sdhci-nand { ralink,group = "sdhci"; - ralink,function = "nand"; + ralink,function = "nand2"; }; }; sdhci_pins: sdhci { diff --git a/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch b/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch index 771de12f171d..23d32681bf77 100644 --- a/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch +++ b/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch @@ -520,7 +520,7 @@ Signed-off-by: John Crispin +} --- /dev/null +++ b/arch/mips/ralink/mt7621.c -@@ -0,0 +1,192 @@ +@@ -0,0 +1,209 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published @@ -555,8 +555,12 @@ Signed-off-by: John Crispin + +#define MT7621_GPIO_MODE_UART1 1 +#define MT7621_GPIO_MODE_I2C 2 -+#define MT7621_GPIO_MODE_UART2 3 -+#define MT7621_GPIO_MODE_UART3 5 ++#define MT7621_GPIO_MODE_UART3_MASK 0x3 ++#define MT7621_GPIO_MODE_UART3_SHIFT 3 ++#define MT7621_GPIO_MODE_UART3_GPIO 1 ++#define MT7621_GPIO_MODE_UART2_MASK 0x3 ++#define MT7621_GPIO_MODE_UART2_SHIFT 5 ++#define MT7621_GPIO_MODE_UART2_GPIO 1 +#define MT7621_GPIO_MODE_JTAG 7 +#define MT7621_GPIO_MODE_WDT_MASK 0x3 +#define MT7621_GPIO_MODE_WDT_SHIFT 8 @@ -566,7 +570,9 @@ Signed-off-by: John Crispin +#define MT7621_GPIO_MODE_PCIE_MASK 0x3 +#define MT7621_GPIO_MODE_PCIE_SHIFT 10 +#define MT7621_GPIO_MODE_PCIE_GPIO 1 -+#define MT7621_GPIO_MODE_MDIO 12 ++#define MT7621_GPIO_MODE_MDIO_MASK 0x3 ++#define MT7621_GPIO_MODE_MDIO_SHIFT 12 ++#define MT7621_GPIO_MODE_MDIO_GPIO 1 +#define MT7621_GPIO_MODE_RGMII1 14 +#define MT7621_GPIO_MODE_RGMII2 15 +#define MT7621_GPIO_MODE_SPI_MASK 0x3 @@ -576,10 +582,18 @@ Signed-off-by: John Crispin +#define MT7621_GPIO_MODE_SDHCI_SHIFT 18 +#define MT7621_GPIO_MODE_SDHCI_GPIO 1 + -+static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart", 0, 1, 2) }; ++static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) }; +static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) }; -+static struct rt2880_pmx_func uart3_grp[] = { FUNC("uart", 0, 5, 4) }; -+static struct rt2880_pmx_func uart2_grp[] = { FUNC("uart", 0, 9, 4) }; ++static struct rt2880_pmx_func uart3_grp[] = { ++ FUNC("uart3", 0, 5, 4), ++ FUNC("i2s", 2, 5, 4), ++ FUNC("spdif3", 3, 5, 4), ++}; ++static struct rt2880_pmx_func uart2_grp[] = { ++ FUNC("uart2", 0, 9, 4), ++ FUNC("pcm", 2, 9, 4), ++ FUNC("spdif2", 3, 9, 4), ++}; +static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) }; +static struct rt2880_pmx_func wdt_grp[] = { + FUNC("wdt rst", 0, 18, 1), @@ -590,28 +604,31 @@ Signed-off-by: John Crispin + FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1) +}; +static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) }; -+static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii", 0, 22, 12) }; ++static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) }; +static struct rt2880_pmx_func spi_grp[] = { + FUNC("spi", 0, 34, 7), -+ FUNC("nand", 2, 34, 8), ++ FUNC("nand1", 2, 34, 7), +}; +static struct rt2880_pmx_func sdhci_grp[] = { + FUNC("sdhci", 0, 41, 8), -+ FUNC("nand", 2, 41, 8), ++ FUNC("nand2", 2, 41, 8), +}; -+static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii", 0, 49, 12) }; ++static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) }; + +static struct rt2880_pmx_group mt7621_pinmux_data[] = { + GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1), + GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C), -+ GRP("uart3", uart2_grp, 1, MT7621_GPIO_MODE_UART2), -+ GRP("uart2", uart3_grp, 1, MT7621_GPIO_MODE_UART3), ++ GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK, ++ MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT), ++ GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK, ++ MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT), + GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG), + GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK, + MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT), + GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK, + MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT), -+ GRP("mdio", mdio_grp, 1, MT7621_GPIO_MODE_MDIO), ++ GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK, ++ MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT), + GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2), + GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK, + MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),