From patchwork Thu Jun 4 15:30:54 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 480781 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from arrakis.dune.hu (arrakis.dune.hu [78.24.191.176]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 6937714016A for ; Fri, 5 Jun 2015 01:33:20 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=googlemail.com header.i=@googlemail.com header.b=Hol0JqaP; dkim-atps=neutral Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id AAAD828C0BE; Thu, 4 Jun 2015 17:30:38 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on arrakis.dune.hu X-Spam-Level: X-Spam-Status: No, score=-1.5 required=5.0 tests=BAYES_00,FREEMAIL_FROM, T_DKIM_INVALID autolearn=unavailable version=3.3.2 Received: from arrakis.dune.hu (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id 7701928C0AC for ; Thu, 4 Jun 2015 17:29:42 +0200 (CEST) X-policyd-weight: using cached result; rate: -8.5 Received: from mail-wg0-f43.google.com (mail-wg0-f43.google.com [74.125.82.43]) by arrakis.dune.hu (Postfix) with ESMTPS for ; Thu, 4 Jun 2015 17:29:37 +0200 (CEST) Received: by wgbgq6 with SMTP id gq6so36533100wgb.3 for ; Thu, 04 Jun 2015 08:31:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qNJ//l36Id6r/4jHd7s/hIeY+hgLswj371nChD5L45k=; b=Hol0JqaPJIlZAIus4HojURONBq8O5TDk2EXdH0Am5dxSWEsGajNUUlB1eN6NKnIqfN zlvCN2q/Unt4Wnfyf0rEIR1hyRkl7dVbLhpn5Kq4gF6aFUo4EoGvDZHlZbvkwaFA3aFM /3/3XSBZrrTrC0HVggWdPdRp800k7OwyYALmeSFfW71hA1QK50qJGdCzBj41AWGsMzWj 35116BmGNNGJT/KdU4uC28lzSFYpigaO7n779No6pfl1zslhKeeaJFkAfGafpvgNyRvn GO3ICYq8RW6Zr8ocYfECzPJqYMG9q9XqJClfZZIqQyD6zwlbvcwvQKIsygdfQKcNGxb2 zMYA== X-Received: by 10.180.91.137 with SMTP id ce9mr8730085wib.76.1433431871545; Thu, 04 Jun 2015 08:31:11 -0700 (PDT) Received: from blackbox.lan (pD957CBAE.dip0.t-ipconnect.de. [217.87.203.174]) by mx.google.com with ESMTPSA id gz3sm3689661wib.0.2015.06.04.08.31.10 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 04 Jun 2015 08:31:10 -0700 (PDT) From: Martin Blumenstingl To: openwrt-devel@lists.openwrt.org Date: Thu, 4 Jun 2015 17:30:54 +0200 Message-Id: <1433431854-16539-3-git-send-email-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.4.2 In-Reply-To: <1433431854-16539-1-git-send-email-martin.blumenstingl@googlemail.com> References: <1433431854-16539-1-git-send-email-martin.blumenstingl@googlemail.com> Subject: [OpenWrt-Devel] [PATCH 3/3] lantiq: Backport gpio-stp-xway to fix the highest bits of the PHY LEDs X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: openwrt-devel-bounces@lists.openwrt.org Sender: "openwrt-devel" This fixes the LAN2 LED on Arcadyan VGV7510KW22. --- .../0043-gpio-stp-xway-fix-phy-mask.patch | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 target/linux/lantiq/patches-3.18/0043-gpio-stp-xway-fix-phy-mask.patch diff --git a/target/linux/lantiq/patches-3.18/0043-gpio-stp-xway-fix-phy-mask.patch b/target/linux/lantiq/patches-3.18/0043-gpio-stp-xway-fix-phy-mask.patch new file mode 100644 index 0000000..967045d --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0043-gpio-stp-xway-fix-phy-mask.patch @@ -0,0 +1,25 @@ +From 08b085a07efe12568d86dff064e6f089e2971744 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Mon, 25 May 2015 22:39:50 +0200 +Subject: gpio-stp-xway: Fix enabling the highest bit of the PHY LEDs + +0x3 only masks two bits, but three bits have to be allowed. This fixes +GPHY0 LED2 (which is the highest bit of phy2) on my board. + +Signed-off-by: Martin Blumenstingl +Acked-by: John Crispin +Signed-off-by: Linus Walleij + +diff --git a/drivers/gpio/gpio-stp-xway.c b/drivers/gpio/gpio-stp-xway.c +index 202361e..6d4148f 100644 +--- a/drivers/gpio/gpio-stp-xway.c ++++ b/drivers/gpio/gpio-stp-xway.c +@@ -58,7 +58,7 @@ + #define XWAY_STP_ADSL_MASK 0x3 + + /* 2 groups of 3 bits can be driven by the phys */ +-#define XWAY_STP_PHY_MASK 0x3 ++#define XWAY_STP_PHY_MASK 0x7 + #define XWAY_STP_PHY1_SHIFT 27 + #define XWAY_STP_PHY2_SHIFT 15 +