diff mbox series

[ovs-dev,v3,01/10] dpdk: Cache result of CPU ISA checks

Message ID 20201118161501.1710801-2-harry.van.haaren@intel.com
State Superseded
Headers show
Series DPIF & MFEX Refactor and AVX512 SIMD optimization | expand

Commit Message

Harry van Haaren Nov. 18, 2020, 4:14 p.m. UTC
As a small optimization, this patch caches the result of a CPU ISA
check from DPDK. Particularly in the case of running the DPCLS
autovalidator (which repeatedly probes subtables) this reduces
the amount of CPU ISA lookups from the DPDK level.

By caching them at the OVS/dpdk.c level, the ISA checks remain
runtime for the CPU where they are executed, but subsequent checks
for the same ISA feature become much cheaper.

Signed-off-by: Harry van Haaren <harry.van.haaren@intel.com>
Signed-off-by: Cian Ferriter <cian.ferriter@intel.com>

---

In theory it is also possible to do the caching of the supported
ISA at the usage site (aka, the DPCLS subtable search implementation)
however that would cause a lot of code-duplication. By caching in
the lower level, we get almost all the benefit with no code duplication.

v3:
- Add braces for single line if statements
- Change wording of comment
---
 lib/dpdk.c | 26 ++++++++++++++++++++++----
 1 file changed, 22 insertions(+), 4 deletions(-)

Comments

0-day Robot Nov. 18, 2020, 5:01 p.m. UTC | #1
Bleep bloop.  Greetings Harry van Haaren, I am a robot and I have tried out your patch.
Thanks for your contribution.

I encountered some error that I wasn't expecting.  See the details below.


checkpatch:
WARNING: Unexpected sign-offs from developers who are not authors or co-authors or committers: Cian Ferriter <cian.ferriter@intel.com>
Lines checked: 63, Warnings: 1, Errors: 0


Please check this out.  If you feel there has been an error, please email aconole@redhat.com

Thanks,
0-day Robot
diff mbox series

Patch

diff --git a/lib/dpdk.c b/lib/dpdk.c
index 2f235a742..ae14d1730 100644
--- a/lib/dpdk.c
+++ b/lib/dpdk.c
@@ -614,13 +614,31 @@  print_dpdk_version(void)
     puts(rte_version());
 }
 
+/* Avoid calling rte_cpu_get_flag_enabled() excessively, by caching the
+ * result of the call for each CPU flag in a static variable. To avoid
+ * allocating large numbers of static variables, use a uint8 as a bitfield.
+ * Note the macro must only return if the ISA check is done and available.
+ */
+#define ISA_CHECK_DONE_BIT (1 << 0)
+#define ISA_AVAILABLE_BIT  (1 << 1)
+
 #define CHECK_CPU_FEATURE(feature, name_str, RTE_CPUFLAG)               \
     do {                                                                \
         if (strncmp(feature, name_str, strlen(name_str)) == 0) {        \
-            int has_isa = rte_cpu_get_flag_enabled(RTE_CPUFLAG);        \
-            VLOG_DBG("CPU flag %s, available %s\n", name_str,           \
-                      has_isa ? "yes" : "no");                          \
-            return true;                                                \
+            static uint8_t isa_check_##RTE_CPUFLAG;                     \
+            int check = isa_check_##RTE_CPUFLAG & ISA_CHECK_DONE_BIT;   \
+            if (OVS_UNLIKELY(!check)) {                                 \
+                int has_isa = rte_cpu_get_flag_enabled(RTE_CPUFLAG);    \
+                VLOG_DBG("CPU flag %s, available %s\n",                 \
+                         name_str, has_isa ? "yes" : "no");             \
+                isa_check_##RTE_CPUFLAG = ISA_CHECK_DONE_BIT;           \
+                if (has_isa) {                                          \
+                    isa_check_##RTE_CPUFLAG |= ISA_AVAILABLE_BIT;       \
+                }                                                       \
+            }                                                           \
+            if (isa_check_##RTE_CPUFLAG & ISA_AVAILABLE_BIT) {          \
+                return true;                                            \
+            }                                                           \
         }                                                               \
     } while (0)