From patchwork Tue Jan 9 17:00:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Himanshu Chauhan X-Patchwork-Id: 1884579 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=HSElyI3d; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=Z/9tGOyB; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=patchwork.ozlabs.org) Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4T8fHn6mKHz1yP3 for ; Wed, 10 Jan 2024 05:15:49 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=H49RhN/CHSSP6YX7ceJtif/njwzMxupw30s30+T7o7o=; b=HSElyI3d2lWHli 3yVLyhlsMoqEZfGdPJgVZrS7XD1Op94CMyv2zKNhDAuy2bKM3Rmrgj93DfIfkro4EVxf0vYAxzf+s IMTy9clH9c7mL4uFFI1szTWzXNvyZyUGtlbyr0XB1QX5T+9Sc+muyuC7xI9/aLptsHuKwhSNvKQr/ /TDWGlGUpKHU2ptyQTq2DCszBGQtTQvzp8vfL4o30kdUk6qqiUfjBbYnSL4oDAGC/kM9IzkCRcb+l LtetQsrzE4mByQ8qIoK00dYjHHiUbqE+QdM9wFWfOy/RopujMZeqbR8vr6r92BE/aY9ae4yegtKyU Lm15EhC+S2ZsXBplVjOg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rNGdT-0096nU-0g; Tue, 09 Jan 2024 18:15:35 +0000 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1rNFSp-008w1C-2T for opensbi@lists.infradead.org; Tue, 09 Jan 2024 17:00:33 +0000 Received: by mail-pg1-x52c.google.com with SMTP id 41be03b00d2f7-58962bf3f89so411170a12.0 for ; Tue, 09 Jan 2024 09:00:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1704819629; x=1705424429; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tyqmepkKiJAseaup+/vtdBiz7Cy5YnTDxB0+hHMzd68=; b=Z/9tGOyB8iU2RS7mUovCEgv0doa+jfV/fKXU8paG0rmI0A3jtXxInwooKd4ylavcZQ GlgCuLANfjoPQm5LcG18pWQhIFQGLgs9buZ1kgxF8qa0Pkrrza7PtS+pyJPn3qJMlDjt DP9FlrIcLzgjOeHuDYAEfMLMpA8sxX8DF7BqFQXvxcQ57xEm8/DSSyNl4lNcPenRuytC R3edTBVuFoQOM/PLQkca61O64DH7XhsYxUF/6hgiHulMCIfaceiDPNKuPoswo7UtvgeM ELHE9BIxJjAoXDvlWBjywoPUlE1wZobRAiptxCB3SXDloqYEDi8jHuCydzG2eFM6TTjx 5Yww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704819629; x=1705424429; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tyqmepkKiJAseaup+/vtdBiz7Cy5YnTDxB0+hHMzd68=; b=Ef5F4JeXawbQHVpdjYaIewc1l24KhkTkzP4rq9Lq5gfkj3Q6Dwdkr9X2yWL6F8Nq70 UtkJeCHe5A9gOC6K2APULM8tSAEoeL2hsK3/OFIevBKFoBkmTOswlaJmcTIH0AyUk+wS oyek5bI6GZZdyM4ZHy9UDGOijJjGY0WVxIpH3nziRxIFM1Oi2aodGdlaLjPbM6KSiK71 XM6DJVpo8sN7XRlHzEfybonpBLDa/ChV+B3nU3sQmI5Fg6Fd0F6IiRGq2ZNdz5kvr1fv lAqhwu83oNFUXOLQl0skZrO7FUN/4grcmWVkJ5a61Y7AJnA9pHQOpcaJh5kVSGg02oul F+Hg== X-Gm-Message-State: AOJu0YwwUAPvySnQJ59BnAL2OJE6Xxj0WjH5354JgJXAJJozy//50J+d W/a76hCoyDp9R6dVm3RMxZU1cyEZoadReNTGfVdVpOZNKkM= X-Google-Smtp-Source: AGHT+IHsKWiV0psel+HNabMOwZc5oZEJZcBpPf4pfvjgxzjl8m4R5oCsegaLZ0T6WpYCTkgF1Sr3Zw== X-Received: by 2002:a05:6a20:13c7:b0:18c:198a:469b with SMTP id ho7-20020a056a2013c700b0018c198a469bmr10120787pzc.6.1704819629054; Tue, 09 Jan 2024 09:00:29 -0800 (PST) Received: from brahaspati.localdomain ([49.37.250.161]) by smtp.gmail.com with ESMTPSA id w8-20020a170902a70800b001d3dff2575fsm2024086plq.52.2024.01.09.09.00.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jan 2024 09:00:28 -0800 (PST) From: Himanshu Chauhan To: opensbi@lists.infradead.org Cc: Anup Patel Subject: [PATCH v3 3/8] include: sbi: Introduce debug trigger register encodings Date: Tue, 9 Jan 2024 22:30:15 +0530 Message-Id: <20240109170020.1731282-4-hchauhan@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240109170020.1731282-1-hchauhan@ventanamicro.com> References: <20240109170020.1731282-1-hchauhan@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240109_090031_832164_E077CD41 X-CRM114-Status: GOOD ( 10.46 ) X-Spam-Score: 0.6 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: This patch introduces Mcontrol and M6 control register encodings along with macros to manipulate them. Signed-off-by: Himanshu Chauhan Reviewed-by: Anup Patel --- include/sbi/riscv_dbtr.h | 249 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 249 [...] Content analysis details: (0.6 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:52c listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.8 UPPERCASE_50_75 message body is 50-75% uppercase X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org This patch introduces Mcontrol and M6 control register encodings along with macros to manipulate them. Signed-off-by: Himanshu Chauhan Reviewed-by: Anup Patel --- include/sbi/riscv_dbtr.h | 249 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 249 insertions(+) create mode 100644 include/sbi/riscv_dbtr.h diff --git a/include/sbi/riscv_dbtr.h b/include/sbi/riscv_dbtr.h new file mode 100644 index 0000000..96c7d3e --- /dev/null +++ b/include/sbi/riscv_dbtr.h @@ -0,0 +1,249 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2023 Ventana Micro System, Inc. + * + * Authors: + * Himanshu Chauhan + */ + +#ifndef __RISCV_DBTR_H__ +#define __RISCV_DBTR_H__ + +#define RV_MAX_TRIGGERS 32 + +enum { + RISCV_DBTR_TRIG_NONE = 0, + RISCV_DBTR_TRIG_LEGACY, + RISCV_DBTR_TRIG_MCONTROL, + RISCV_DBTR_TRIG_ICOUNT, + RISCV_DBTR_TRIG_ITRIGGER, + RISCV_DBTR_TRIG_ETRIGGER, + RISCV_DBTR_TRIG_MCONTROL6, +}; + +#define RV_DBTR_BIT(_prefix, _name) \ + RV_DBTR_##_prefix##_##_name##_BIT + +#define RV_DBTR_BIT_MASK(_prefix, _name) \ + RV_DBTR_##_prefix##_name##_BIT_MASK + +#define RV_DBTR_DECLARE_BIT(_prefix, _name, _val) \ + RV_DBTR_BIT(_prefix, _name) = _val + +#define RV_DBTR_DECLARE_BIT_MASK(_prefix, _name, _width) \ + RV_DBTR_BIT_MASK(_prefix, _name) = \ + (((1UL << _width) - 1) << RV_DBTR_BIT(_prefix, _name)) + +#define CLEAR_DBTR_BIT(_target, _prefix, _bit_name) \ + __clear_bit(RV_DBTR_BIT(_prefix, _bit_name), &_target) + +#define SET_DBTR_BIT(_target, _prefix, _bit_name) \ + __set_bit(RV_DBTR_BIT(_prefix, _bit_name), &_target) + +/* Trigger Data 1 */ +enum { + RV_DBTR_DECLARE_BIT(TDATA1, DATA, 0), +#if __riscv_xlen == 64 + RV_DBTR_DECLARE_BIT(TDATA1, DMODE, 59), + RV_DBTR_DECLARE_BIT(TDATA1, TYPE, 60), +#elif __riscv_xlen == 32 + RV_DBTR_DECLARE_BIT(TDATA1, DMODE, 27), + RV_DBTR_DECLARE_BIT(TDATA1, TYPE, 28), +#else + #error "Unknown __riscv_xlen" +#endif +}; + +enum { +#if __riscv_xlen == 64 + RV_DBTR_DECLARE_BIT_MASK(TDATA1, DATA, 59), +#elif __riscv_xlen == 32 + RV_DBTR_DECLARE_BIT_MASK(TDATA1, DATA, 27), +#else + #error "Unknown __riscv_xlen" +#endif + RV_DBTR_DECLARE_BIT_MASK(TDATA1, DMODE, 1), + RV_DBTR_DECLARE_BIT_MASK(TDATA1, TYPE, 4), +}; + +/* MC - Match Control Type Register */ +enum { + RV_DBTR_DECLARE_BIT(MC, LOAD, 0), + RV_DBTR_DECLARE_BIT(MC, STORE, 1), + RV_DBTR_DECLARE_BIT(MC, EXEC, 2), + RV_DBTR_DECLARE_BIT(MC, U, 3), + RV_DBTR_DECLARE_BIT(MC, S, 4), + RV_DBTR_DECLARE_BIT(MC, RES2, 5), + RV_DBTR_DECLARE_BIT(MC, M, 6), + RV_DBTR_DECLARE_BIT(MC, MATCH, 7), + RV_DBTR_DECLARE_BIT(MC, CHAIN, 11), + RV_DBTR_DECLARE_BIT(MC, ACTION, 12), + RV_DBTR_DECLARE_BIT(MC, SIZELO, 16), + RV_DBTR_DECLARE_BIT(MC, TIMING, 18), + RV_DBTR_DECLARE_BIT(MC, SELECT, 19), + RV_DBTR_DECLARE_BIT(MC, HIT, 20), +#if __riscv_xlen >= 64 + RV_DBTR_DECLARE_BIT(MC, SIZEHI, 21), +#endif +#if __riscv_xlen == 64 + RV_DBTR_DECLARE_BIT(MC, MASKMAX, 53), + RV_DBTR_DECLARE_BIT(MC, DMODE, 59), + RV_DBTR_DECLARE_BIT(MC, TYPE, 60), +#elif __riscv_xlen == 32 + RV_DBTR_DECLARE_BIT(MC, MASKMAX, 21), + RV_DBTR_DECLARE_BIT(MC, DMODE, 27), + RV_DBTR_DECLARE_BIT(MC, TYPE, 28), +#else + #error "Unknown __riscv_xlen" +#endif +}; + +enum { + RV_DBTR_DECLARE_BIT_MASK(MC, LOAD, 1), + RV_DBTR_DECLARE_BIT_MASK(MC, STORE, 1), + RV_DBTR_DECLARE_BIT_MASK(MC, EXEC, 1), + RV_DBTR_DECLARE_BIT_MASK(MC, U, 1), + RV_DBTR_DECLARE_BIT_MASK(MC, S, 1), + RV_DBTR_DECLARE_BIT_MASK(MC, RES2, 1), + RV_DBTR_DECLARE_BIT_MASK(MC, M, 1), + RV_DBTR_DECLARE_BIT_MASK(MC, MATCH, 4), + RV_DBTR_DECLARE_BIT_MASK(MC, CHAIN, 1), + RV_DBTR_DECLARE_BIT_MASK(MC, ACTION, 4), + RV_DBTR_DECLARE_BIT_MASK(MC, SIZELO, 2), + RV_DBTR_DECLARE_BIT_MASK(MC, TIMING, 1), + RV_DBTR_DECLARE_BIT_MASK(MC, SELECT, 1), + RV_DBTR_DECLARE_BIT_MASK(MC, HIT, 1), +#if __riscv_xlen >= 64 + RV_DBTR_DECLARE_BIT_MASK(MC, SIZEHI, 2), +#endif + RV_DBTR_DECLARE_BIT_MASK(MC, MASKMAX, 6), + RV_DBTR_DECLARE_BIT_MASK(MC, DMODE, 1), + RV_DBTR_DECLARE_BIT_MASK(MC, TYPE, 4), +}; + +/* MC6 - Match Control 6 Type Register */ +enum { + RV_DBTR_DECLARE_BIT(MC6, LOAD, 0), + RV_DBTR_DECLARE_BIT(MC6, STORE, 1), + RV_DBTR_DECLARE_BIT(MC6, EXEC, 2), + RV_DBTR_DECLARE_BIT(MC6, U, 3), + RV_DBTR_DECLARE_BIT(MC6, S, 4), + RV_DBTR_DECLARE_BIT(MC6, RES2, 5), + RV_DBTR_DECLARE_BIT(MC6, M, 6), + RV_DBTR_DECLARE_BIT(MC6, MATCH, 7), + RV_DBTR_DECLARE_BIT(MC6, CHAIN, 11), + RV_DBTR_DECLARE_BIT(MC6, ACTION, 12), + RV_DBTR_DECLARE_BIT(MC6, SIZE, 16), + RV_DBTR_DECLARE_BIT(MC6, TIMING, 20), + RV_DBTR_DECLARE_BIT(MC6, SELECT, 21), + RV_DBTR_DECLARE_BIT(MC6, HIT, 22), + RV_DBTR_DECLARE_BIT(MC6, VU, 23), + RV_DBTR_DECLARE_BIT(MC6, VS, 24), +#if __riscv_xlen == 64 + RV_DBTR_DECLARE_BIT(MC6, DMODE, 59), + RV_DBTR_DECLARE_BIT(MC6, TYPE, 60), +#elif __riscv_xlen == 32 + RV_DBTR_DECLARE_BIT(MC6, DMODE, 27), + RV_DBTR_DECLARE_BIT(MC6, TYPE, 28), +#else + #error "Unknown __riscv_xlen" +#endif +}; + +enum { + RV_DBTR_DECLARE_BIT_MASK(MC6, LOAD, 1), + RV_DBTR_DECLARE_BIT_MASK(MC6, STORE, 1), + RV_DBTR_DECLARE_BIT_MASK(MC6, EXEC, 1), + RV_DBTR_DECLARE_BIT_MASK(MC6, U, 1), + RV_DBTR_DECLARE_BIT_MASK(MC6, S, 1), + RV_DBTR_DECLARE_BIT_MASK(MC6, RES2, 1), + RV_DBTR_DECLARE_BIT_MASK(MC6, M, 1), + RV_DBTR_DECLARE_BIT_MASK(MC6, MATCH, 4), + RV_DBTR_DECLARE_BIT_MASK(MC6, CHAIN, 1), + RV_DBTR_DECLARE_BIT_MASK(MC6, ACTION, 4), + RV_DBTR_DECLARE_BIT_MASK(MC6, SIZE, 4), + RV_DBTR_DECLARE_BIT_MASK(MC6, TIMING, 1), + RV_DBTR_DECLARE_BIT_MASK(MC6, SELECT, 1), + RV_DBTR_DECLARE_BIT_MASK(MC6, HIT, 1), + RV_DBTR_DECLARE_BIT_MASK(MC6, VU, 1), + RV_DBTR_DECLARE_BIT_MASK(MC6, VS, 1), +#if __riscv_xlen == 64 + RV_DBTR_DECLARE_BIT_MASK(MC6, DMODE, 1), + RV_DBTR_DECLARE_BIT_MASK(MC6, TYPE, 4), +#elif __riscv_xlen == 32 + RV_DBTR_DECLARE_BIT_MASK(MC6, DMODE, 1), + RV_DBTR_DECLARE_BIT_MASK(MC6, TYPE, 4), +#else + #error "Unknown __riscv_xlen" +#endif +}; + +#define RV_DBTR_SET_TDATA1_TYPE(_t1, _type) \ + do { \ + _t1 &= ~RV_DBTR_BIT_MASK(TDATA1, TYPE); \ + _t1 |= (((unsigned long)_type \ + << RV_DBTR_BIT(TDATA1, TYPE)) \ + & RV_DBTR_BIT_MASK(TDATA1, TYPE)); \ + }while (0); + +#define RV_DBTR_SET_MC_TYPE(_t1, _type) \ + do { \ + _t1 &= ~RV_DBTR_BIT_MASK(MC, TYPE); \ + _t1 |= (((unsigned long)_type \ + << RV_DBTR_BIT(MC, TYPE)) \ + & RV_DBTR_BIT_MASK(MC, TYPE)); \ + }while (0); + +#define RV_DBTR_SET_MC6_TYPE(_t1, _type) \ + do { \ + _t1 &= ~RV_DBTR_BIT_MASK(MC6, TYPE); \ + _t1 |= (((unsigned long)_type \ + << RV_DBTR_BIT(MC6, TYPE)) \ + & RV_DBTR_BIT_MASK(MC6, TYPE)); \ + }while (0); + +#define RV_DBTR_SET_MC_EXEC(_t1) \ + SET_DBTR_BIT(_t1, MC, EXEC) + +#define RV_DBTR_SET_MC_LOAD(_t1) \ + SET_DBTR_BIT(_t1, MC, LOAD) + +#define RV_DBTR_SET_MC_STORE(_t1) \ + SET_DBTR_BIT(_t1, MC, STORE) + +#define RV_DBTR_SET_MC_SIZELO(_t1, _val) \ + do { \ + _t1 &= ~RV_DBTR_BIT_MASK(MC, SIZELO); \ + _t1 |= ((_val << RV_DBTR_BIT(MC, SIZELO)) \ + & RV_DBTR_BIT_MASK(MC, SIZELO)); \ + } while(0); + +#define RV_DBTR_SET_MC_SIZEHI(_t1, _val) \ + do { \ + _t1 &= ~RV_DBTR_BIT_MASK(MC, SIZEHI); \ + _t1 |= ((_val << RV_DBTR_BIT(MC, SIZEHI)) \ + & RV_DBTR_BIT_MASK(MC, SIZEHI)); \ + } while(0); + +#define RV_DBTR_SET_MC6_EXEC(_t1) \ + SET_DBTR_BIT(_t1, MC6, EXEC) + +#define RV_DBTR_SET_MC6_LOAD(_t1) \ + SET_DBTR_BIT(_t1, MC6, LOAD) + +#define RV_DBTR_SET_MC6_STORE(_t1) \ + SET_DBTR_BIT(_t1, MC6, STORE) + +#define RV_DBTR_SET_MC6_SIZE(_t1, _val) \ + do { \ + _t1 &= ~RV_DBTR_BIT_MASK(MC6, SIZE); \ + _t1 |= ((_val << RV_DBTR_BIT(MC6, SIZE)) \ + & RV_DBTR_BIT_MASK(MC6, SIZE)); \ + } while(0); + +typedef unsigned long riscv_dbtr_tdata1_mcontrol_t; +typedef unsigned long riscv_dbtr_tdata1_mcontrol6_t; +typedef unsigned long riscv_dbtr_tdata1_t; + +#endif /* __RISCV_DBTR_H__ */