[v3,2/8] include: sbi: Add TINFO debug trigger CSR

Message ID	20240109170020.1731282-3-hchauhan@ventanamicro.com
State	Accepted
Headers	show Return-Path: <opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org> From: Himanshu Chauhan <hchauhan@ventanamicro.com> To: opensbi@lists.infradead.org Cc: Anup Patel <anup@brainfault.org> Subject: [PATCH v3 2/8] include: sbi: Add TINFO debug trigger CSR Date: Tue, 9 Jan 2024 22:30:14 +0530 Message-Id: <20240109170020.1731282-3-hchauhan@ventanamicro.com> In-Reply-To: <20240109170020.1731282-1-hchauhan@ventanamicro.com> References: <20240109170020.1731282-1-hchauhan@ventanamicro.com> MIME-Version: 1.0 preview: Add the missing TINFO debug trigger CSR. Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> --- include/sbi/riscv_encoding.h \| 1 + 1 file changed, 1 insertion(+) Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:62d listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "opensbi" <opensbi-bounces@lists.infradead.org> Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org
Series	Introduce support for SBI Debug Trigger Extension \| expand [v3,0/8] Introduce support for SBI Debug Trigger Extension [v3,1/8] include: sbi: Introduce common endianess conversion macro [v3,2/8] include: sbi: Add TINFO debug trigger CSR [v3,3/8] include: sbi: Introduce debug trigger register encodings [v3,4/8] lib: sbi: Detect support of debug triggers [v3,5/8] lib: sbi: Introduce the SBI debug triggers extension support [v3,6/8] include: sbi: Add SBI debug trigger extension related defines [v3,7/8] lib: sbi: Implement SBI debug trigger extension [v3,8/8] lib: sbi: Print number of debug triggers found

Message ID

20240109170020.1731282-3-hchauhan@ventanamicro.com

State

Accepted

Headers

From: Himanshu Chauhan <hchauhan@ventanamicro.com>
To: opensbi@lists.infradead.org
Cc: Anup Patel <anup@brainfault.org>
Subject: [PATCH v3 2/8] include: sbi: Add TINFO debug trigger CSR
Date: Tue,  9 Jan 2024 22:30:14 +0530
Message-Id: <20240109170020.1731282-3-hchauhan@ventanamicro.com>
In-Reply-To: <20240109170020.1731282-1-hchauhan@ventanamicro.com>
References: <20240109170020.1731282-1-hchauhan@ventanamicro.com>
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Precedence: list
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Series

Introduce support for SBI Debug Trigger Extension | expand

Commit Message

Himanshu Chauhan Jan. 9, 2024, 5 p.m. UTC

Add the missing TINFO debug trigger CSR.

Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
 include/sbi/riscv_encoding.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
index f20df76..e74cc0d 100644
--- a/include/sbi/riscv_encoding.h
+++ b/include/sbi/riscv_encoding.h
@@ -686,6 +686,7 @@ 
 #define CSR_TDATA1			0x7a1
 #define CSR_TDATA2			0x7a2
 #define CSR_TDATA3			0x7a3
+#define CSR_TINFO			0x7a4
 
 /* Debug Mode Registers */
 #define CSR_DCSR			0x7b0

[v3,2/8] include: sbi: Add TINFO debug trigger CSR

Commit Message

Patch