From patchwork Thu Oct 13 02:29:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu Chien Peter Lin X-Patchwork-Id: 1689349 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=2XJa0rXV; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4MntnT5lqfz23jn for ; Thu, 13 Oct 2022 13:31:41 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=1zKrxTDGWl3eY5kFM2JWDb3mfYI6AOBNBqNrMij8OIM=; b=2XJa0rXVFIfi5I CxhBn4eaOvVf8Ni/Xjv48PYBAaAEK3iN1DRUmnKuktYjo2o8Nd81orOksCpHlr2ElGYc8cwyLrEEm FiEVSqmI8x19dZnWCWkvCjljPsjt5huOZoS4TT2fbpnLbDq3LV9NwwS5ZeXSj6EHZ/QoZppFVKxMt jmsq1AL7m9ukklTGaaCmqUm48ONv6c2g4KqMVOXcILOuTI7/1PUHbSP3UAbZcaIC3cJ1wQyv4iLd5 za9ytUlopTWGNqbUJokCaZRYhhwfTHjwSNVy2+9FpPl9e+YUd+OA6b6S1b8cLH8/IvCNG1d84oKXO AYD2GQ/5/PTCC/X2yLng==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oio0N-00ALfm-Cf; Thu, 13 Oct 2022 02:31:27 +0000 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oio0K-00ALdF-55 for opensbi@lists.infradead.org; Thu, 13 Oct 2022 02:31:26 +0000 Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 29D2Ulcq047937; Thu, 13 Oct 2022 10:30:47 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from atcfdc88.andestech.com (10.0.15.120) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Thu, 13 Oct 2022 10:30:44 +0800 From: Yu Chien Peter Lin To: CC: , , , Yu Chien Peter Lin , Anup Patel Subject: [PATCH v3 08/13] lib: utils/reset: Add Andes fdt reset driver support Date: Thu, 13 Oct 2022 10:29:46 +0800 Message-ID: <20221013022951.5206-9-peterlin@andestech.com> X-Mailer: git-send-email 2.38.GIT In-Reply-To: <20221013022951.5206-1-peterlin@andestech.com> References: <20221013022951.5206-1-peterlin@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.120] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 29D2Ulcq047937 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221012_193124_506838_C89A1AC1 X-CRM114-Status: GOOD ( 18.46 ) X-Spam-Score: 0.4 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. 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Content preview: Add ATCWDT200 as reset device of AE350 platform, this driver requires SMU to program the reset vector registers before triggering WDT software restart signal. dts example: smu@f0100000 { compatible = "andestech,atcsmu"; reg = <0x00000000 0xf0100000 0x00000000 0x00001000>; }; Content analysis details: (0.4 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 TVD_RCVD_IP Message was received from an IP address -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.4 RDNS_DYNAMIC Delivered to internal network by host with dynamic-looking rDNS X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Add ATCWDT200 as reset device of AE350 platform, this driver requires SMU to program the reset vector registers before triggering WDT software restart signal. dts example: smu@f0100000 { compatible = "andestech,atcsmu"; reg = <0x00000000 0xf0100000 0x00000000 0x00001000>; }; wdt: wdt@f0500000 { compatible = "andestech,atcwdt200"; reg = <0x00000000 0xf0500000 0x00000000 0x00001000>; interrupts = <3 4>; interrupt-parent = <&plic0>; clock-frequency = <15000000>; }; Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Anup Patel --- Changes v2 -> v3 - No change since v2 --- lib/utils/reset/Kconfig | 4 + lib/utils/reset/fdt_reset_atcwdt200.c | 122 ++++++++++++++++++++++++++ lib/utils/reset/objects.mk | 3 + platform/andes/ae350/Kconfig | 2 + platform/andes/ae350/platform.c | 3 + 5 files changed, 134 insertions(+) create mode 100644 lib/utils/reset/fdt_reset_atcwdt200.c diff --git a/lib/utils/reset/Kconfig b/lib/utils/reset/Kconfig index 2e83ff6..0e0c2c1 100644 --- a/lib/utils/reset/Kconfig +++ b/lib/utils/reset/Kconfig @@ -9,6 +9,10 @@ config FDT_RESET if FDT_RESET +config FDT_RESET_ATCWDT200 + bool "Andes WDT FDT reset driver" + default n + config FDT_RESET_GPIO bool "GPIO FDT reset driver" depends on FDT_GPIO diff --git a/lib/utils/reset/fdt_reset_atcwdt200.c b/lib/utils/reset/fdt_reset_atcwdt200.c new file mode 100644 index 0000000..91acc9f --- /dev/null +++ b/lib/utils/reset/fdt_reset_atcwdt200.c @@ -0,0 +1,122 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2022 Andes Technology Corporation + * + * Authors: + * Yu Chien Peter Lin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ATCWDT200_WP_NUM 0x5aa5 +#define WREN_REG 0x18 +#define CTRL_REG 0x10 +#define RST_TIME_OFF 8 +#define RST_TIME_MSK (0x3 << RST_TIME_OFF) +#define RST_CLK_128 (0 << RST_TIME_OFF) +#define RST_CLK_256 (1 << RST_TIME_OFF) +#define RST_CLK_512 (2 << RST_TIME_OFF) +#define RST_CLK_1024 (3 << RST_TIME_OFF) +#define INT_TIME_OFF 4 +#define INT_TIME_MSK (0xf << INT_TIME_OFF) +#define INT_CLK_64 (0 << INT_TIME_OFF) +#define INT_CLK_256 (1 << INT_TIME_OFF) +#define INT_CLK_1024 (2 << INT_TIME_OFF) +#define INT_CLK_2048 (3 << INT_TIME_OFF) +#define INT_CLK_4096 (4 << INT_TIME_OFF) +#define INT_CLK_8192 (5 << INT_TIME_OFF) +#define INT_CLK_16384 (6 << INT_TIME_OFF) +#define INT_CLK_32768 (7 << INT_TIME_OFF) +#define RST_EN (1 << 3) +#define INT_EN (1 << 2) +#define CLK_PCLK (1 << 1) +#define WDT_EN (1 << 0) + +#define FLASH_BASE 0x80000000ULL +#define SMU_RESET_VEC_LO_OFF 0x50 +#define SMU_RESET_VEC_HI_OFF 0x60 +#define SMU_HARTn_RESET_VEC_LO(n) (SMU_RESET_VEC_LO_OFF + (n * 0x4)) +#define SMU_HARTn_RESET_VEC_HI(n) (SMU_RESET_VEC_HI_OFF + (n * 0x4)) + +static volatile char *wdt_addr; +static volatile char *smu_addr; + +static int ae350_system_reset_check(u32 type, u32 reason) +{ + switch (type) { + case SBI_SRST_RESET_TYPE_COLD_REBOOT: + return 1; + case SBI_SRST_RESET_TYPE_SHUTDOWN: + case SBI_SRST_RESET_TYPE_WARM_REBOOT: + default: + return 0; + } +} + +static void ae350_system_reset(u32 type, u32 reason) +{ + const struct sbi_platform *plat = sbi_platform_thishart_ptr(); + + for (int i = 0; i < sbi_platform_hart_count(plat); i++) { + writel(FLASH_BASE, smu_addr + SMU_HARTn_RESET_VEC_LO(i)); + writel(FLASH_BASE >> 32, smu_addr + SMU_HARTn_RESET_VEC_HI(i)); + } + + /* Program WDT control register */ + writew(ATCWDT200_WP_NUM, wdt_addr + WREN_REG); + writel(INT_CLK_32768 | INT_EN | RST_CLK_128 | RST_EN | WDT_EN, + wdt_addr + CTRL_REG); + + sbi_hart_hang(); +} + +static struct sbi_system_reset_device atcwdt200_reset = { + .name = "atcwdt200", + .system_reset_check = ae350_system_reset_check, + .system_reset = ae350_system_reset, +}; + +static int atcwdt200_reset_init(void *fdt, int nodeoff, + const struct fdt_match *match) +{ + uint64_t reg_addr; + int rc; + + rc = fdt_get_node_addr_size(fdt, nodeoff, 0, ®_addr, NULL); + if (rc < 0 || !reg_addr) + return SBI_ENODEV; + + wdt_addr = (volatile char *)(unsigned long)reg_addr; + + /* + * The reset device requires smu to program the reset + * vector for each hart. + */ + if (fdt_parse_compat_addr(fdt, ®_addr, "andestech,atcsmu")) + return SBI_ENODEV; + + smu_addr = (volatile char *)(unsigned long)reg_addr; + + sbi_system_reset_add_device(&atcwdt200_reset); + + return 0; +} + +static const struct fdt_match atcwdt200_reset_match[] = { + { .compatible = "andestech,atcwdt200" }, + {}, +}; + +struct fdt_reset fdt_reset_atcwdt200 = { + .match_table = atcwdt200_reset_match, + .init = atcwdt200_reset_init, +}; diff --git a/lib/utils/reset/objects.mk b/lib/utils/reset/objects.mk index 8a50dd0..c9f851c 100644 --- a/lib/utils/reset/objects.mk +++ b/lib/utils/reset/objects.mk @@ -10,6 +10,9 @@ libsbiutils-objs-$(CONFIG_FDT_RESET) += reset/fdt_reset.o libsbiutils-objs-$(CONFIG_FDT_RESET) += reset/fdt_reset_drivers.o +carray-fdt_reset_drivers-$(CONFIG_FDT_RESET_ATCWDT200) += fdt_reset_atcwdt200 +libsbiutils-objs-$(CONFIG_FDT_RESET_ATCWDT200) += reset/fdt_reset_atcwdt200.o + carray-fdt_reset_drivers-$(CONFIG_FDT_RESET_GPIO) += fdt_poweroff_gpio carray-fdt_reset_drivers-$(CONFIG_FDT_RESET_GPIO) += fdt_reset_gpio libsbiutils-objs-$(CONFIG_FDT_RESET_GPIO) += reset/fdt_reset_gpio.o diff --git a/platform/andes/ae350/Kconfig b/platform/andes/ae350/Kconfig index f6f50eb..8486f08 100644 --- a/platform/andes/ae350/Kconfig +++ b/platform/andes/ae350/Kconfig @@ -8,6 +8,8 @@ config PLATFORM_ANDES_AE350 select FDT_SERIAL_UART8250 select FDT_TIMER select FDT_TIMER_PLMT + select FDT_RESET + select FDT_RESET_ATCWDT200 default y if PLATFORM_ANDES_AE350 diff --git a/platform/andes/ae350/platform.c b/platform/andes/ae350/platform.c index 79736c0..c6a8eeb 100644 --- a/platform/andes/ae350/platform.c +++ b/platform/andes/ae350/platform.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include "platform.h" @@ -37,6 +38,8 @@ static int ae350_final_init(bool cold_boot) if (!cold_boot) return 0; + fdt_reset_init(); + fdt = fdt_get_address(); fdt_fixups(fdt);