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10 Sep 2021 04:40:42 +0800 IronPort-SDR: 4lldQIGtrX452KW22SRIJUpmZESBfaw0Gm9tgyXqKAVyMn1Nm9kbJPQ1gTvnCFMmMXOgCfq10R ssWjTkgERfNenOXoiZjILy7doSxx1REJ1QRiXHEmelfWeUX1lTy+upt+GyLXyUN7EPni6VzON7 2OX37XzrevNif/PZ7kZAC+6vPyVhkBMjiqu7dQi795qQgN+wJ5GpONqDus4W/BadAdXxcqXh9+ EJwHTSjsBLK+K/cYSlAPOr6WbgOol7EMYyy8bC3fqQAphTYHTl5mHjCXL5oDArxwcNjX4NfcCL 8Ifh564MOxvMd8LmVffMCUtG Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2021 13:15:38 -0700 IronPort-SDR: OhCuFT6/f5Y5/SCeRNxTZ1YdLAKSUHo4jufcPohTTPSvkbMIgDJ3khP8C9dsFskw08OVM0VY+0 DGLroM46ww1vNj0oWtL1hRRkSRmTgadHk1ePJzBMGWfohowZ4enHUrGb3+ZThmT35FbTjJpBMJ C4x2NyTEBb2nYDqvdRZ2SwlNkBPObuIp1CVcCuZTwURUPID9sy+C3NwhWF89ztak+wpYl/Pblu F8lR2Pd+kdda8zM7crHK9PxzeFS0NmqUVhlpXFAoRj2QBsb2ydXdC09uMdwWNdwn0UDh9/rBTj jL4= WDCIronportException: Internal Received: from unknown (HELO hulk.wdc.com) ([10.225.167.73]) by uls-op-cesaip02.wdc.com with ESMTP; 09 Sep 2021 13:40:43 -0700 From: Atish Patra To: opensbi@lists.infradead.org Cc: Atish Patra , anup.patel@wdc.com Subject: [RFC PATCH 8/9] lib:sbi: Reset the mhpmevent value upon counter reset Date: Thu, 9 Sep 2021 13:40:30 -0700 Message-Id: <20210909204031.1239254-9-atish.patra@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210909204031.1239254-1-atish.patra@wdc.com> References: <20210909204031.1239254-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210909_134048_480906_4C237DD4 X-CRM114-Status: GOOD ( 11.91 ) X-Spam-Score: -2.5 (--) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: The hardware solely relies on the event selector value in mhpmevent to figure out what event to monitor using that counter. It should be reset when counter reset happens. Signed-off-by: Atish Patra --- lib/sbi/sbi_pmu.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) Content analysis details: (-2.5 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.141.245 listed in list.dnswl.org] 0.0 SPF_NONE SPF: sender does not publish an SPF Record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org The hardware solely relies on the event selector value in mhpmevent to figure out what event to monitor using that counter. It should be reset when counter reset happens. Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- lib/sbi/sbi_pmu.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c index 20f78c75200e..f33842052a46 100644 --- a/lib/sbi/sbi_pmu.c +++ b/lib/sbi/sbi_pmu.c @@ -368,6 +368,20 @@ static int pmu_ctr_stop_fw(uint32_t cidx, uint32_t fw_evt_code) return 0; } +static int pmu_reset_hw_mhpmevent(int ctr_idx) +{ + if (ctr_idx < 3 || ctr_idx >= SBI_PMU_HW_CTR_MAX) + return SBI_EFAIL; +#if __riscv_xlen == 32 + csr_write_num(CSR_MCOUNTINHIBIT + ctr_idx, 0); + csr_write_num(CSR_MHPMEVENT3H + ctr_idx - 3, 0); +#else + csr_write_num(CSR_MCOUNTINHIBIT + ctr_idx, 0); +#endif + + return 0; +} + int sbi_pmu_ctr_stop(unsigned long cbase, unsigned long cmask, unsigned long flag) { @@ -391,8 +405,10 @@ int sbi_pmu_ctr_stop(unsigned long cbase, unsigned long cmask, else ret = pmu_ctr_stop_hw(cbase); - if (!ret && (flag & SBI_PMU_STOP_FLAG_RESET)) + if (flag & SBI_PMU_STOP_FLAG_RESET) { active_events[hartid][cbase] = SBI_PMU_EVENT_IDX_INVALID; + pmu_reset_hw_mhpmevent(cbase); + } } return ret;