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Tue, 18 Aug 2020 04:07:59 +0000 From: Anup Patel To: Atish Patra , Alistair Francis Subject: [PATCH v3 2/2] lib: sbi: Handle the case where MTVAL has illegal instruction address Date: Tue, 18 Aug 2020 09:37:28 +0530 Message-Id: <20200818040728.528426-2-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200818040728.528426-1-anup.patel@wdc.com> References: <20200818040728.528426-1-anup.patel@wdc.com> X-ClientProxiedBy: BM1PR0101CA0015.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:18::25) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (103.20.29.9) by BM1PR0101CA0015.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:18::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3283.15 via Frontend Transport; Tue, 18 Aug 2020 04:07:56 +0000 X-Mailer: git-send-email 2.25.1 X-Originating-IP: [103.20.29.9] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 92a95ce1-ed4f-43c3-eda5-08d8432c4b64 X-MS-TrafficTypeDiagnostic: DM5PR04MB3772: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:6430; 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To handle above case, we fix sbi_illegal_insn_handler() without any impact on RISC-V v1.10 (or higher) systems. This achieved by exploiting the fact that program counter (and instruction address) is always 2-byte aligned in RISC-V world. Signed-off-by: Anup Patel Tested-by: Heinrich Schuchardt Reviewed-by: Bin Meng Reviewed-by: Atish Patra --- lib/sbi/sbi_illegal_insn.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/lib/sbi/sbi_illegal_insn.c b/lib/sbi/sbi_illegal_insn.c index 0e5523f..9af3d24 100644 --- a/lib/sbi/sbi_illegal_insn.c +++ b/lib/sbi/sbi_illegal_insn.c @@ -118,13 +118,22 @@ int sbi_illegal_insn_handler(ulong insn, struct sbi_trap_regs *regs) { struct sbi_trap_info uptrap; + /* + * We only deal with 32-bit (or longer) illegal instructions. If we + * see instruction is zero OR instruction is 16-bit then we fetch and + * check the instruction encoding using unprivilege access. + * + * The program counter (PC) in RISC-V world is always 2-byte aligned + * so handling only 32-bit (or longer) illegal instructions also help + * the case where MTVAL CSR contains instruction address for illegal + * instruction trap. + */ + if (unlikely((insn & 3) != 3)) { - if (insn == 0) { - insn = sbi_get_insn(regs->mepc, &uptrap); - if (uptrap.cause) { - uptrap.epc = regs->mepc; - return sbi_trap_redirect(regs, &uptrap); - } + insn = sbi_get_insn(regs->mepc, &uptrap); + if (uptrap.cause) { + uptrap.epc = regs->mepc; + return sbi_trap_redirect(regs, &uptrap); } if ((insn & 3) != 3) return truly_illegal_insn(insn, regs);