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[RFC,0/1] RISC-V Sspesa: OpenSBI firmware support

Message ID 20260817160006.3310109-1-mayuresh.chitale@oss.qualcomm.com
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Series RISC-V Sspesa: OpenSBI firmware support | expand

Message

Mayuresh Chitale Aug. 17, 2026, 4 p.m. UTC 
This OpenSBI series enables firmware support for the Sspesa (Precise
Event Sample Attribution) extension.

Sspesa exposes the shpmspc and shpmsdata CSRs, and S-mode access to
these CSRs is gated by menvcfg.CDE. This patch detects the extension
and sets menvcfg.CDE so that Linux can read the sample CSRs.

Reproducing the full setup:

Sspesa support requires three projects: OpenSBI, Linux and QEMU. The
matching branches are:

  OpenSBI: https://github.com/mdchitale/opensbi/tree/riscv_sspesa_rfc_v1
  Linux:   https://github.com/mdchitale/linux/tree/riscv_sspesa_rfc_v1
  QEMU:    https://github.com/mdchitale/qemu/tree/riscv_sspesa_rfc_v1

To test Sspesa, build OpenSBI, Linux and QEMU from the branches above,
then boot Linux with:

  qemu-system-riscv64 -nographic -machine virt -smp 2 -m 2G \
    -cpu rv64,sscofpmf=on,sspesa=on \
    -bios /path/to/fw_dynamic.bin -kernel /path/to/Image \
    -drive file=/path/to/rootfs.img,id=hd0,format=raw,if=none \
    -device virtio-blk-device,drive=hd0 \
    -append "root=/dev/vda rw console=ttyS0 earlycon=sbi"

With all three in place, a counter overflow (e.g. 'perf record -e
cycles -c 1000000 -- <workload>') is attributed using the
hardware-provided sample PC (shpmspc) and counter ID (shpmsdata)
instead of falling back to epc.

Mayuresh Chitale (1):
  lib/sbi: Enable menvcfg.CDE for Sspesa

 include/sbi/riscv_encoding.h | 4 ++++
 include/sbi/sbi_hart.h       | 2 ++
 lib/sbi/sbi_hart.c           | 7 ++++++-
 3 files changed, 12 insertions(+), 1 deletion(-)