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[v2,0/2] Register Zicntr in FDT when emulating is possible

Message ID 20250418144758.2633-1-ziyao@disroot.org
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Series Register Zicntr in FDT when emulating is possible | expand

Message

Yao Zi April 18, 2025, 2:47 p.m. UTC 
OpenSBI is capable of emulating time CSR on HARTs without a full Zicntr
extension. Previously, we hardcoded Zicntr extension in the devicetree
for these cores, like JH7110 in mainline Linux[1]. This doesn't reflect
the hardware and may confuse pre-SBI bootloaders, like U-Boot running in
M-Mode.

To solve the issue, let's register Zicntr in FDT dynamically for cores
supporting it by SBI emulation, allowing pre-SBI stages to detect Zicntr
availability reliably with riscv,isa-extensions.

[1]: https://elixir.bootlin.com/linux/v6.14-rc3/source/arch/riscv/boot/dts/starfive/jh7110.dtsi#L61

Changed from v1
- Zicntr detection
  - Introduce a bitmap to sbi_hart_features instead of using pseudo-
    extensions to represent availability of CSRs
  - Change possibly misleading abbreviation "RO" to "read-only" in
    commit message
- FDT fixup
  - Don't register zicntr to (legacy) devicetrees where harts don't come
    with a riscv,isa-extensions property

Yao Zi (2):
  lib: sbi: hart: Detect existence of cycle and instret CSRs for Zicntr
  lib: utils: fdt: Claim Zicntr if time CSR emulation is possible

 include/sbi/sbi_hart.h    |  9 +++++++++
 lib/sbi/sbi_hart.c        | 35 ++++++++++++++++++++++++++++-------
 lib/utils/fdt/fdt_fixup.c | 33 ++++++++++++++++++++++++++++++++-
 3 files changed, 69 insertions(+), 8 deletions(-)