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[u-boot,1/1] ARM: dts: ast2600 msx4: switch to rgmii-id phy mode

Message ID 20260504044702.2613879-2-andhsieh@nvidia.com
State New
Headers show
Series aspeed: msx4: switch phy-mode to rgmii-id | expand

Commit Message

Ender Hsieh May 4, 2026, 4:47 a.m. UTC 
Switch the MAC0 phy-mode to "rgmii-id" so the PHY handles internal
RX/TX delay, and drop the SCU mac0-clk-delay block since SoC-side
delay is no longer needed.

Coordinated with the kernel-side change adding the &mac0/&mdio3
nodes with phy-mode = "rgmii-id" to the MSX4 board dts in
mainline Linux.

Signed-off-by: Ender Hsieh <andhsieh@nvidia.com>
---
 arch/arm/dts/ast2600-msx4-bmc-nvidia.dts | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm/dts/ast2600-msx4-bmc-nvidia.dts b/arch/arm/dts/ast2600-msx4-bmc-nvidia.dts
index 9b64f7e734..9df5e74c98 100644
--- a/arch/arm/dts/ast2600-msx4-bmc-nvidia.dts
+++ b/arch/arm/dts/ast2600-msx4-bmc-nvidia.dts
@@ -62,7 +62,7 @@ 
 
 &mac0 {
 	status = "okay";
-	phy-mode = "rgmii";
+	phy-mode = "rgmii-id";
 	phy-handle = <&ethphy3>;
 
 	pinctrl-names = "default";
@@ -82,12 +82,6 @@ 
 	};
 };
 
-&scu {
-	mac0-clk-delay = <0x1d 0x0a
-			  0x1d 0x0a
-			  0x1d 0x0a>;
-};
-
 &sdrammc {
 	clock-frequency = <400000000>;
 	aspeed,ecc-enabled;